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Initial circuit | Timing overview | Best stage effort | Library mapping | Gate retiming | Input buffering | Better accuracy | Prior art | Summary | Conclusions | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

## Calculating the best stage effortAccording to the theory of logical effort, the fastest circuit occurs when each stage bears an equal effort. That is, the values ofgh in the expression
d = τ × (p+gh)
all have the same value.
The best stage effort is the one that minimises the delay,
and is used to determine the best number of stages in a logic
network.
We label the best stage effort ρ and it occurs when the
parasitic delay of an inverter, p+ρ × (1 - ln(ρ)) = 0
_{inv}
If the inverter parasitic delay is 0, i.e. an ideal inverter,
then the best stage effort occurs when ρ = ## Using the best stage effort to calculate fixed gate timingIn the method of the patent,
an initial fixed delay is given to each function.
This delay equals that of the best stage effort:
d = τ × (p + ρ)
## Consideration of the errors applying logical effort to non-inverting gatesAn advantage of the logical effort theory is the simplification of timing information so that each function has one set of timing numbers. If the standard cell library is sufficiently rich, then the predicted timing will be met by choosing cells which are close to the desired drive strength.
This really only works for single stage inverting cells. For 2-stage
non-inverting cells, the approximation is poor once the gain C
exceeds a value of about 4. The graph on the right shows a good
clustering of parasitic delay and logical effort around a mean for the
inverting NAND and NOR gates and inverters, but a worse clustering for the
non-inverting AND and OR gates and buffers. For these gates,
the weak drive strengths have less delay when lightly loaded,
shown by a smaller value of parasitic delay, _{IN}p.
But when heavily loaded,
the weak drive strengths will have a larger delay, as shown by the
larger value of logic effort, g.
The
There are also 3 different types of 2-XOR gate implementation.
Here average values are taken from all the variants which
leads to more substantial errors between the estimated and
actual values. For example, there is a 15% difference
between the estimated and actual parasitic delay for the
worst case cell, the |
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24-JUL-05 |