Initial circuit Timing overview Best stage effort Library mapping Gate retiming Input buffering Better accuracy Prior art Summary Conclusions

On July 1, 2004, Magma wrote to Synopsys suggesting that Synopsys might be infringing on three of Magma's patents. These patents describe algorithms on which Magma's well publicised Fixed Timing Methodology is based.

Previously Synopsys had described as limited Magma's claims about this methodology. But when presented with this letter, Synopsys claimed that two of the patents in dispute belonged to them because the inventor had worked for Synopsys when the original algorithm was invented.

Magma's case looked weak when the inventor, Lukas van Ginneken admitted that this was true. However, Synopsys had threatened van Ginneken with a $100 million lawsuit, a threat which was withdrawn after his admission. A confession made under duress isn't so credible as one freely made.

The original Magma letter implied that, through these patents, they owned gain based synthesis. But gain based logic design was not invented by Magma, has been around since at least the early 90's, and is well described in the book on Logical Effort by Sutherland, Sproull and Harris. So what is the original idea in the patents under dispute, if any? The links above are a detailed paper on the synthesis algorithm applied to the 4-bit adder circuit on the right. The Summary page provides a brief technical overview and the Conclusions page presents the reports conclusions.

The first version of the paper was released on July 31, 2005 and a second version on August 6, 2005. The main difference is in the mapping algorithms used to choose the standard cells, a task which is difficult to do well.

The patents can also be downloaded in a convenient PDF format.

Unoptimised 4-bit adder circuit to be improved with 350ps critical path delay and 35fF max input capacitance using the 0.13-micron vsclib. initial adder

Generalized Theory of Logical Effort for Look-Up Table Based Delay Models Using Capacitance Ratio, U.S. Patent No. 6,253,361

Timing Closure Methodology, U.S Patent No. 6,453,446

Timing Closure Methodology, U.S Patent No. 6,725,438