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Initial circuit | Timing overview | Best stage effort | Library mapping | Gate retiming | Input buffering | Better accuracy | Prior art | Summary | Conclusions |

## Prop-Ramp modelThe simple delay model for CMOS logic is a so-called Prop-Ramp model. The delay is:
The Ramp. Consistent units here are delay measured in ps;
capacitance in fF and Ramp in kΩ. In the experiments
here, the delay is the average of rise and fall delays.
The delay is also not modified by input slopes, but in a more
sophisticated system both factors would be included.
## Expressions for logical effortFor single stage inverting functions, the theory of Logical Effort shows that the delay of the function is the sum of the parasitic delay and the effort:
C_{IN}τ is the technology time constant, defined as the average drive resistance of an inverter multiplied by its input capacitance. For the vsclib in 0.13um, τ = 9.7ps.
By comparing both expressions for delay, we can see that C
_{IN}
The term C is
also called the _{IN}gain or electrical effort.
For a single stage it is represented by the symbol h.
For a path, the symbol H is used.
The logical effort of a gate is represented by
The term |

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24-JUL-05 |