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Initial circuit | Timing overview | Best stage effort | Library mapping | Gate retiming | Input buffering | Better accuracy | Prior art | Summary | Conclusions | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

## Two coefficient area mappingThe patent refers to a single variableC
derived from the library data for each function and used to
link the delay of a function to its area.
As already seen,
this leads to significant inaccuracies in the area estimate.
_{S}
A better estimate of the area can be made by using
two coefficients for the area approximation. This
isn't described in the patent, but is an extension of
the ideas given there. We replace the expression
for the delay
C×_{S}A))with d = τ × (p +
C /(_{OUT}C+_{S0}C×_{S1}A))
The two fitted curves for pin
The equation linking the estimated cell area to the
delay
d/τ -p)-C
}/_{S0}C
_{S1}
Values for C
are averaged over all the cells for a function.
The constant timing model sets each cell's delay,
and from this and the load capacitance _{S1}C
an estimate of its area according to the equation above.
The area is mapped to a drive strength as shown in the
example below for pin _{OUT}a of a 2-XOR gate.
The adjusted xor2v0x05.
The graph below for an inverter shows that the fit between actual and estimated areas is much better than before, especially for the weaker drive strengths.
The values of the single coefficient C is the
drive per unit area, so is higher for an inverter
and lower for more complex gates.
_{S}
The values of C are determined by a library
analysis and are shown in the tables below.
These are used to estimate the area of each
cell in the 4-bit adder using the area equation above.
_{S1}
One can observe a problem with the methodology by
comparing the coefficients for the ## Netlist comparisonThe drive strengths produced by mapping with one area coefficient and by two are the same for the adder with unbuffered inputs. For this circuit, the more accurate mapping has no benefit.
For the adder with buffered inputs there is an improvement
in the final schematic. The area estimates produced by either of the coefficients for this circuit is good, as shown in the table below.
The area estimate can give values which are larger than the largest cell or smaller than the smallest cell. In this case, the actual largest or smallest area is used instead. |
Fitting single and double area coefficients
for pin a of a 2-NAND gate
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Fig 7a. Buffered adder delays with
(i) fixed stage effort of f=3.6 used for initial timing;
(ii) each gate delay compressed or stretched to meet critical path;
(iii) wireload of 6fF per fanout;
(iv) gain limit of 5 used for non-inverting gates;
(v) single area coefficient C to map drive strength;
(vi) timing from vsclib cells._{S} | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Fig 7b. Buffered adder delays with
(i) fixed stage effort of f=3.6 used for initial timing;
(ii) each gate delay compressed or stretched to meet critical path;
(iii) wireload of 6fF per fanout;
(iv) two area coefficients C to map drive strength;
(v) timing using library averages._{S} | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Fig 7c. Buffered adder delays with
(i) fixed stage effort of f=3.6 used for initial timing;
(ii) each gate delay compressed or stretched to meet critical path;
(iii) wireload of 6fF per fanout;
(iv) gain limit of 5 used for non-inverting gates;
(v) two area coefficients C,_{S0}C to map drive strength;
(vi) timing from vsclib cells._{S1} |

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5-AUG-05 |