or2 standard cell family

 2-I/P OR gate
or2 symbol
2 I/P OR gates designed with large (v0 version) and small (v4 version) input stages, and the or2v7x2 which uses an N transistor pull-up on the output to speed up the rise delay. This leads to a temporary high short circuit current which is about 30% higher than the equivalent or2v0x2 cell. The stage effort is 1.5 for the or2v0x05, 1.8 for the or2v0x1, 2.2 for the or2v0x2, 2.4 for the or2v0x3, 2.6 for the or2v0x4, 3.0 for the or2v0x8 and 4.0 for the or2v4x1. The v0 cells are optimised for speed with typical wireload values, while the v4 cell is optimised for a zero wireload capacitance.
The nd2ab cells do the same function faster but use more power.
z:(a+b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
or2v0x05 1.7  40 2.20  0.54  13.0  3.0f  74  4.96  97  3.92
or2v0x1 1.7  40 2.20  0.69  15.0  3.4f  75  3.31  91  2.65
or2v4x1 1.7  40 2.20  0.57  13.2  2.0f  67  3.30 127  2.67
or2v0x2 1.7  40 2.20  0.99  21.5  4.3f  77  2.12  94  1.68
or2v7x2 2.3  56 3.08 1.16  26.0  5.1f  62  1.19  92  1.68
or2v0x3 2.7  64 3.52 1.34  26.2  5.3f  74  1.49  90  1.17
or2v0x4 2.7  64 3.52 1.73  34.0  6.1f  76  1.06  95  0.85
or2v0x8 4.3 104 5.72 2.98  60.7  9.5f  83  0.56 101  0.46
or2v0x05
 
Effort
FO4 Log.
a /\
¯_ 2.09
b /\
¯_ 1.99
or2v0x05 schematic or2v0x05 standard cell layout
or2v0x1
 
Effort
FO4 Log.
a /\
¯_ 1.92
b /\
¯_ 1.76
or2v0x1 schematic or2v0x1 standard cell layout
or2v4x1
 
Effort
FO4 Log.
a /\
¯_ 1.88
b /\
¯_ 1.73
or2v4x1 schematic or2v4x1 standard cell layout
or2v0x2
 
Effort
FO4 Log.
a /\
¯_ 1.85
b /\
¯_ 1.69
or2v0x2 schematic or2v0x2 standard cell layout
or2v7x2
 
Effort
FO4 Log.
a /\
¯_ 1.83
b /\
¯_ 1.53
or2v7x2 schematic or2v7x2 standard cell layout
or2v0x3
 
Effort
FO4 Log.
a /\
¯_ 1.77
b /\
¯_ 1.58
or2v0x3 schematic or2v0x3 standard cell layout
or2v0x4
 
Effort
FO4 Log.
a /\
¯_ 1.74
b /\
¯_ 1.56
or2v0x4 schematic or2v0x4 standard cell layout
or2v0x8
 
Effort
FO4 Log.
a /\
¯_ 1.76
b /\
¯_ 1.60
or2v0x8 schematic or2v0x8 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008