nd2 standard cell family

2-I/P NAND gate
nd2 symbol
nd2 effort graph Single stage 2-I/P NAND gates. 7 drive strengths with four choices of P:N transistor ratio. The v0 version has a P:N ratio of about 2; in the v3 version it is 1, in the v4 version it is 4 and in the v5 version it is 2.6, the actual value of µ, the conductivity ratio between the N and P transistors.
nd2v6x3 is an alternate and slower layout version of the nd2v0x3. It is slower because the the input transistors are distributed across the cell, which means they must be connected by relatively long wires which gives the pins a higher capacitance.
The graph on the right shows the FO4 effort values of the different NAND gates.
z:(a*b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd2v0x05 1.3  32 1.76  0.27   3.2  1.8f  45  7.41  34  5.30
nd2v3x05 1.3  32 1.76  0.43   5.1  3.2f  51  5.95  25  2.31
nd2v5x05 1.3  32 1.76  0.23   4.2  2.3f  43  4.94  36  4.61
nd2v0x1 1.3  32 1.76  0.46   5.5  3.0f  45  4.24  33  3.10
nd2v3x1 2.0  48 2.64  0.72   7.3  5.1f  47  3.50  23  1.41
nd2v4x1 1.3  32 1.76  0.51   5.6  2.9f  40  3.30  43  4.59
nd2v5x1 1.3  32 1.76  0.58   6.5  3.4f  42  3.12  37  3.07
nd2v0x2 1.3  32 1.76  0.79   8.7  4.8f  43  2.47  33  1.85
nd2v3x2 2.0  48 2.64 1.02  10.6  7.1f  47  2.48  24  0.97
nd2v4x2 2.3  56 3.08  0.89   9.1  4.9f  38  1.87  42  2.84
nd2v5x2 1.3  32 1.76  0.85   9.1  5.0f  41  2.12  36  2.04
nd2v0x3 2.3  56 3.08 1.18  11.9  7.0f  42  1.65  32  1.23
nd2v6x3 2.3  56 3.08 1.18  12.7  7.2f  43  1.65  33  1.23
nd2v3x3 2.7  64 3.52 1.44  16.1 10.5f  49  1.75  25  0.68
nd2v4x3 2.3  56 3.08 1.28  13.0  7.9f  36  1.11  42  1.94
nd2v5x3 2.3  56 3.08 1.25  12.2  7.0f  40  1.48  35  1.42
nd2v0x4 2.3  56 3.08 1.57  16.2  9.5f  42  1.23  32  0.93
nd2v3x4 3.7  88 4.84 2.03  21.3 14.3f  48  1.24  24  0.49
nd2v4x4 3.0  72 3.96 1.73  17.3  9.8f  38  0.96  41  1.42
nd2v5x4 2.3  56 3.08 1.71  17.2  9.9f  40  1.06  35  1.03
nd2v0x6 3.0  72 3.96 2.36  25.1 14.2f  43  0.82  33  0.61
nd2v4x6 4.0  96 5.28 2.54  24.9 14.2f  38  0.66  41  0.97
nd2v5x6 3.0  72 3.96 2.47  25.3 14.4f  41  0.73  36  0.72
nd2v0x8 4.0  96 5.28 3.14  32.2 19.1f  42  0.62  32  0.46
nd2v4x8 4.7 112 6.16 3.49  34.6 19.5f  38  0.48  41  0.71
nd2v5x8 4.0  96 5.28 3.42  34.5 19.9f  40  0.53  35  0.51
nd2v0x05
 
Effort
FO4 Log.
a /\ 1.24 1.29
¯_
b /\ 1.23 1.35
¯_
nd2v0x05 schematic nd2v0x05 standard cell layout
nd2v3x05
 
Effort
FO4 Log.
a /\ 1.38 1.49
¯_
b /\ 1.29 1.52
¯_
nd2v3x05 schematic nd2v3x05 standard cell layout
nd2v5x05
 
Effort
FO4 Log.
a /\ 1.23 1.29
¯_
b /\ 1.20 1.29
¯_
nd2v5x05 schematic nd2v5x05 standard cell layout
nd2v0x1
 
Effort
FO4 Log.
a /\ 1.22 1.27
¯_
b /\ 1.19 1.28
¯_
nd2v0x1 schematic nd2v0x1 standard cell layout
nd2v3x1
 
Effort
FO4 Log.
a /\ 1.34 1.48
¯_
b /\ 1.22 1.46
¯_
nd2v3x1 schematic nd2v3x1 standard cell layout
nd2v4x1
 
Effort
FO4 Log.
a /\ 1.28 1.37
¯_
b /\ 1.26 1.35
¯_
nd2v4x1 schematic nd2v4x1 standard cell layout
nd2v5x1
 
Effort
FO4 Log.
a /\ 1.20 1.25
¯_
b /\ 1.18 1.24
¯_
nd2v5x1 schematic nd2v5x1 standard cell layout
nd2v0x2
 
Effort
FO4 Log.
a /\ 1.18 1.21
¯_
b /\ 1.14 1.20
¯_
nd2v0x2 schematic nd2v0x2 standard cell layout
nd2v3x2
 
Effort
FO4 Log.
a /\ 1.35 1.49
¯_
b /\ 1.22 1.43
¯_
nd2v3x2 schematic nd2v3x2 standard cell layout
nd2v4x2
 
Effort
FO4 Log.
a /\ 1.25 1.35
¯_
b /\ 1.24 1.35
¯_
nd2v4x2 schematic nd2v4x2 standard cell layout
nd2v5x2
 
Effort
FO4 Log.
a /\ 1.18 1.22
¯_
b /\ 1.15 1.21
¯_
nd2v5x2 schematic nd2v5x2 standard cell layout
nd2v0x3
 
Effort
FO4 Log.
a /\ 1.19 1.21
¯_
b /\ 1.11 1.18
¯_
nd2v0x3 schematic nd2v0x3 standard cell layout
nd2v6x3
 
Effort
FO4 Log.
a /\ 1.21 1.27
¯_
b /\ 1.14 1.21
¯_
nd2v6x3 schematic nd2v6x3 standard cell layout
nd2v3x3
 
Effort
FO4 Log.
a /\ 1.35 1.47
¯_
b /\ 1.26 1.49
¯_
nd2v3x3 schematic nd2v3x3 standard cell layout
nd2v4x3
 
Effort
FO4 Log.
a /\ 1.21 1.26
¯_
b /\ 1.25 1.40
¯_
nd2v4x3 schematic nd2v4x3 standard cell layout
nd2v5x3
 
Effort
FO4 Log.
a /\ 1.19 1.21
¯_
b /\ 1.12 1.19
¯_
nd2v5x3 schematic nd2v5x3 standard cell layout
nd2v0x4
 
Effort
FO4 Log.
a /\ 1.19 1.25
¯_
b /\ 1.12 1.19
¯_
nd2v0x4 schematic nd2v0x4 standard cell layout
nd2v3x4
 
Effort
FO4 Log.
a /\ 1.35 1.49
¯_
b /\ 1.22 1.44
¯_
nd2v3x4 schematic nd2v3x4 standard cell layout
nd2v4x4
 
Effort
FO4 Log.
a /\ 1.27 1.39
¯_
b /\ 1.24 1.36
¯_
nd2v4x4 schematic nd2v4x4 standard cell layout
nd2v5x4
 
Effort
FO4 Log.
a /\ 1.18 1.25
¯_
b /\ 1.13 1.20
¯_
nd2v5x4 schematic nd2v5x4 standard cell layout
nd2v0x6
 
Effort
FO4 Log.
a /\ 1.18 1.22
¯_
b /\ 1.13 1.19
¯_
nd2v0x6 schematic nd2v0x6 standard cell layout
nd2v4x6
 
Effort
FO4 Log.
a /\ 1.26 1.38
¯_
b /\ 1.23 1.34
¯_
nd2v4x6 schematic nd2v4x6 standard cell layout
nd2v5x6
 
Effort
FO4 Log.
a /\ 1.18 1.24
¯_
b /\ 1.15 1.22
¯_
nd2v5x6 schematic nd2v5x6 standard cell layout
nd2v0x8
 
Effort
FO4 Log.
a /\ 1.19 1.25
¯_
b /\ 1.12 1.20
¯_
nd2v0x8 schematic nd2v0x8 standard cell layout
nd2v4x8
 
Effort
FO4 Log.
a /\ 1.26 1.38
¯_
b /\ 1.23 1.34
¯_
nd2v4x8 schematic nd2v4x8 standard cell layout
nd2v5x8
 
Effort
FO4 Log.
a /\ 1.19 1.26
¯_
b /\ 1.14 1.21
¯_
nd2v5x8 schematic nd2v5x8 standard cell layout