an2 standard cell family

 2-I/P AND gate
an2 symbol
2 I/P AND gate designed with large (v0 version) and small (v4 version) input stages. The stage effort is 1.4 for the an2v0x05, 1.6 for the an2v0x1, 2.0 for the an2v0x2, 2.2 for the an2v0x3, 2.4 for the an2v0x4, 2.7 for the an2v0x6, 2.9 for the an2v0x8 and 4.0 for the an2v4 cells. All the cells use a P/N ratio of about 2. The v0 cells are optimised for speed with typical wireload values, while the v4 cells are optimised for a zero wireload capacitance.
The first to second stage step up ratio of the v0 cells is being changed. For the changed cells, the old cell has been copied to the v2 version.
z:(a*b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
an2v0x05 1.7  40 2.20  0.54  11.0  2.5f  65  4.96  85  3.85
an2v0x1 1.7  40 2.20  0.74  15.2  3.0f  68  3.30  86  2.56
an2v4x1 1.7  40 2.20  0.52  13.0  1.6f  83  3.31 115  2.61
an2v0x2 1.7  40 2.20 1.07  21.3  3.9f  73  2.13  82  1.65
an2v2x2 1.7  40 2.20 1.04  21.1  3.8f  69  2.13  86  1.66
an2v4x2 1.7  40 2.20  0.75  18.3  1.9f  91  2.14 116  1.70
an2v0x3 2.3  56 3.08 1.35  26.4  4.4f  70  1.49  89  1.15
an2v0x4 2.3  56 3.08 1.78  34.5  5.3f  73  1.07  90  0.83
an2v4x4 2.3  56 3.08 1.46  31.5  3.1f  91  1.07 111  0.85
an2v0x6 3.3  80 4.40 2.44  48.0  6.8f  75  0.74  93  0.57
an2v0x8 4.0  96 5.28 3.27  64.5  8.6f  76  0.53  96  0.41
an2v4x8 3.3  80 4.40 2.68  56.0  5.6f  88  0.57 110  0.46
an2v0x05
 
Effort
FO4 Log.
a /\
¯_ 1.81
b /\
¯_ 1.71
an2v0x05 schematic an2v0x05 standard cell layout
an2v0x1
 
Effort
FO4 Log.
a /\
¯_ 1.71
b /\
¯_ 1.61
an2v0x1 schematic an2v0x1 standard cell layout
an2v4x1
 
Effort
FO4 Log.
a /\
¯_ 1.81
b /\
¯_ 1.69
an2v4x1 schematic an2v4x1 standard cell layout
an2v0x2
 
Effort
FO4 Log.
a /\
¯_ 1.61
b /\
¯_ 1.53
an2v0x2 schematic an2v0x2 standard cell layout
an2v2x2
 
Effort
FO4 Log.
a /\
¯_ 1.61
b /\
¯_ 1.52
an2v2x2 schematic an2v2x2 standard cell layout
an2v4x2
 
Effort
FO4 Log.
a /\
¯_ 1.78
b /\
¯_ 1.69
an2v4x2 schematic an2v4x2 standard cell layout
an2v0x3
 
Effort
FO4 Log.
a /\
¯_ 1.55
b /\
¯_ 1.47
an2v0x3 schematic an2v0x3 standard cell layout
an2v0x4
 
Effort
FO4 Log.
a /\
¯_ 1.53
b /\
¯_ 1.46
an2v0x4 schematic an2v0x4 standard cell layout
an2v4x4
 
Effort
FO4 Log.
a /\
¯_ 1.69
b /\
¯_ 1.63
an2v4x4 schematic an2v4x4 standard cell layout
an2v0x6
 
Effort
FO4 Log.
a /\
¯_ 1.53
b /\
¯_ 1.47
an2v0x6 schematic an2v0x6 standard cell layout
an2v0x8
 
Effort
FO4 Log.
a /\
¯_ 1.53
b /\
¯_ 1.47
an2v0x8 schematic an2v0x8 standard cell layout
an2v4x8
 
Effort
FO4 Log.
a /\
¯_ 1.65
b /\
¯_ 1.59
an2v4x8 schematic an2v4x8 standard cell layout
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology.   Copyright © 2005-2008 Graham Petley.  11 JAN 2008