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3 I/P AND gate designed with large (v0 version) and small (v4 version) input stages. The stage effort is 1.5 for the an3v0x05, 1.8 for the an3v0x1, 2.1 for the an3v0x2, 2.6 for the an3v0x4 and 4.0 for the an3v4 cells. All the cells use a P/N ratio of about 2.33 for the NAND gates, which gives equal size P and N transistors. The v0 cells are optimised for speed with typical wireload values, while the v4 cells are optimised for a zero wireload capacitance. |