The following directory structure has been used for the sclib. The locations can be set by the user by assigning a value to environment variable ALLIANCE_MOS (I use /home/dev/alliance).

downloaded sclib /home/cad/alliance-4.0.6/share/cells/sclib
private copy of sclib $ALLIANCE_MOS/cells/sclib
0fF wireload macros for BOOG $ALLIANCE_MOS/vbe/sclib100_0_min_macros
0fF wireload macros for LOON $ALLIANCE_MOS/vbe/sclib100_0_macros
0fF wireload VBE files $ALLIANCE_MOS/vbe/sclib100_0
0fF wireload min VBE files with x1 inverter  $ALLIANCE_MOS/vbe/sclib100_0_min_x1
0fF wireload min VBE files with x2 inverter $ALLIANCE_MOS/vbe/sclib100_0_min_x2
0fF wireload min VBE files with x4 inverter $ALLIANCE_MOS/vbe/sclib100_0_min_x4
0fF wireload min VBE files with x8 inverter $ALLIANCE_MOS/vbe/sclib100_0_min_x8
45fF wireload macros for BOOG $ALLIANCE_MOS/vbe/sclib100_45_min_macros
45fF wireload macros for LOON $ALLIANCE_MOS/vbe/sclib100_45_macros
45fF wireload VBE files $ALLIANCE_MOS/vbe/sclib100_45
45fF wireload min VBE files with x1 inverter  $ALLIANCE_MOS/vbe/sclib100_45_min_x1
45fF wireload min VBE files with x2 inverter $ALLIANCE_MOS/vbe/sclib100_45_min_x2
45fF wireload min VBE files with x4 inverter $ALLIANCE_MOS/vbe/sclib100_45_min_x4
45fF wireload min VBE files with x8 inverter $ALLIANCE_MOS/vbe/sclib100_45_min_x8
netlists for macros $ALLIANCE_MOS/vbe/sclib_netlist

  1. The downloaded sclib is not touched. The directory can also be added to the $MBK_CATA_LIB variable so that the CATAL file used is the original one.
  2. The files in the private sclib are copied and edited with a script. The script is mainly concerned with the layout files, but also includes the VBE file corrections and changes to the logic description of the cells.
  3. The VBE macros with 0fF and 45fF wireload timing have their own directories.
  4. LOON synthesis with 45fF wireloads needs to find all the VBE files in one directory. The 45fF wireload directory contains (i) the 0fF wireload files from the original sclib modified by adding 45fF to the input capacitance; and (ii) the VBE files in sclib100_45_macros copied across. Similarly for 0fF wireload synthesis.
  5. BOOG synthesis needs to find all its files in one directory. It uses a directory with min drive strength only cells, except for the inverters. We have eight directories, one for each drive strength inverter and choice of wireload. The VBE files in sclib100_45_min_macros are copied over to the 45fF wireload directories, and similary for the 0fF wireload. BOOG synthesis can be done with the 0fF or 45fF wireload min drive strength libraries. The 0fF gave better results here.
  6. The VBE files in the 0fF wireload directory sclib100_0 are copies of the private sclib ones. It is convenient to have a copy so that they can be edited for experimentation.
  7. The content of the macro and netlist directories is created by the user.
  8. The macro netlists can be accessed by making sure that the MBK_CATA_LIB environment variable, which is the search path for netlists, includes sclib_netlist:

$ echo $MBK_CATA_LIB

A script convert_cell in the private sclib directory edits each sclib cell as it is copied across. The directory contents are made by

  1. copying across the contents of the downloaded sclib
  2. converting each cell with the convert_cell script

The conversion lists each cell, edits it by prefixing with string convert_cell and then executing it. Then in the 0fF wireload directory we have a script copycells which copies the VBE files from the private sclib and the locally created macros.

In the 45fF wireload directory we have a script makecell which copies a cell from the 0fF wireload directory and adds 45fF to the input pin capacitances. We also have a file copycells which copies across the logic macros and runs makecell for each cell.

The minimum drive strength directory sclib100_45_min_x1 for BOOG contains a script copycells which copies across the cells we want visible to BOOG for its synthesis. The other BOOG directories have similar scripts.

The sequence to refresh the cells in each of the synthesis directories is:

1 $ cd $ALLIANCE_MOS/cells/sclib
2 $ cp -p /home/cad/alliance-4.0.6/share/cells/sclib/* .
3 $ ls -1 *.ap | sed 's|^\(.*\)\.ap$|./convert_cell \1|' | bash
4 $ cd $ALLIANCE_MOS/vbe/sclib100_0
5 $ ./copycells
6 $ cd $ALLIANCE_MOS/vbe/sclib100_45
7 $ ./copycells
8 $ cd $ALLIANCE_MOS/vbe/sclib100_45_min_x1
9 $ ./copycells
10 $ cd $ALLIANCE_MOS/vbe/sclib100_45_min_x2
11 $ ./copycells
12 $ cd $ALLIANCE_MOS/vbe/sclib100_45_min_x4
13 $ ./copycells
14 $ cd $ALLIANCE_MOS/vbe/sclib100_45_min_x8
15 $ ./copycells
16 $ cd $ALLIANCE_MOS/vbe/sclib100_0_min_x1
17 $ ./copycells
18 $ cd $ALLIANCE_MOS/vbe/sclib100_0_min_x2
19 $ ./copycells
20 $ cd $ALLIANCE_MOS/vbe/sclib100_0_min_x4
21 $ ./copycells
22 $ cd $ALLIANCE_MOS/vbe/sclib100_0_min_x8
23 $ ./copycells

sclib100_0_min_macros and sclib100_45_min_macros directory contents


sclib100_0_macros and sclib100_45_macros directory contents

a2drv_y.vbe   mx2drv_y.vbe  noa4p_y.vbe    xr2drv_y.vbe
crydrv_y.vbe  mx3p_y.vbe    nxr2drv_y.vbe
drvp_y.vbe    noa3p_y.vbe   o2drv_y.vbe

sclib_netlist directory contents

a2drv_y.vst   drvp_y.vst    noa3p_y.vst    o2drv_y.vst
cryb_y.vst    mx2drv_y.vst  noa4p_y.vst    xr2drv_y.vst
crydrv_y.vst  mx3p_y.vst    nxr2drv_y.vst

sclib100_0_min_x4 and sclib100_45_min_x4 directory contents

a2_y.vbe      mx2_y.vbe   no2_y.vbe    sum_y.vbe
a3_y.vbe      mx3_y.vbe   no3_y.vbe    tie_y.vbe
a4_y.vbe      mx4_y.vbe   noa3_y.vbe   tsn_y.vbe
annup_y.vbe   na2_y.vbe   noa4_y.vbe   tsp_y.vbe
cmx2_y.vbe    na3_y.vbe   noue4_y.vbe  ts_y.vbe
copycells     na4_y.vbe   nxr2_y.vbe   xr2_y.vbe
cryb_y.vbe    nao3_y.vbe  o2_y.vbe     zero_y.vbe
cry_y.vbe     nao4_y.vbe  o3_y.vbe
ms2dp2_y.vbe  ndrv_y.vbe  one_y.vbe
msdp2_y.vbe   nmx2_y.vbe  p1_y.vbe