A succession of improvements have been made to the library and synthesis flow with the objective of improving the critical path of the synthesised netlist. The measured timing has also been changed to include delays due to the input and output capacitances.

The Alliance 8×8 multiplier from the examples directory has been used to measure progress, and the results so far are shown on the right.

As mentioned before, these critical path timings do not include the delays due to wire capacitance. Normal practice is to estimate the wire capacitance and include its effect into the delay calculation. If the estimate is good, then the delays post layout will be close to the estimated values.

The Alliance software cannot handle estimated wire delays, or wireloads. What we can do is add an estimated wire capacitance to each cell's input pin so that the larger pin cap is considered during synthesis.

  boog opt loon opt delay delay gates max
rin cout rin cout
0 0 1.5kΩ 300f
Original Alliance lib and synthesis 2 2 23873 25042 1674 8
Original Alliance lib and best synthesis 4 2 20592 22789 1961 26
Library corrections and carry cell 4 2 17852 20014 2036 26
Min drive strength BOOG synthesis 4 2 18510 19754 2021 63
4 2 17091 18131 2259 20
4 2 17511 18119 2260 20