A netlist's speed can be improved by giving the inputs a large fanin. The delay of driving all this capacitance is transferred to the gate driving the input. We want to create a netlist that considers this delay and chooses a fanin which minimises the overall delay. As a design objective, we also want the maximum fanin to be less than or equal to four, or a user defined different value.

This is done by assigning an input resistance to each input. I have chosen a value of 1.5kΩ. This is slightly higher than the output resistance of an x2 drive strength gate which is about 1.3kΩ or 1.3ns/pF in the sclib.

The resistance is put into a LAX file like loon_1500_000_1.lax which for also sets the optimisation level (1 in this case).

We can retime the netlists from the Alliance synthesis by adding a LOON run with opt level 0 and a 1.5kΩ input impedance.

1 $ OLD_ALLIANCE=/home/cad/alliance-4.0.6
2 $ MBK_TARGET_LIB=$OLD_ALLIANCE/share/cells/sclib
3 $ boog -l loon_0000_000_4 multi8 multi8_o
4 $ loon -l loon_0000_000_2 multi8_o multi8_1
5 $ loon -l loon_1500_000_0 multi8_1 multi8

The extra delay (eg. 22022 cf 20592) is the product of the input resistance and capacitance.

Critical Path Delay (ps)
Opt level BOOG
LOON 0 1 2 4
0  29845   29273   29665   30599 
1  29067   27862   28510   30005 
2  corrupt  24067   24423   22022 
4  24783   24647   24352   22270 

Alternatively, we can synthesise the multiplier using BOOG and LOON with a LAX file setting the input impedance. I find that BOOG netlists are faster with the input impedance set to zero, but LOON is able to use the input impedance to generate a faster netlist.

1 $ boog -l loon_0000_000_2 multi8 multi8_o
2 $ loon -l loon_1500_000_2 multi8_o multi8       

Critical Path Delay (ps)
Opt level BOOG
LOON 0 1 2 4
0  29845   29273   29665   30599 
1  29067   27862   28510   30005 
2  corrupt  24145   24275   29407 
4  26215   24618   24635   29407 

The timing differences are shown in the table below. For LOON opt levels 0 and 1, the critical paths are the same. For LOON opt levels 2 and 4 there is an increase except for two conditions.

Critical Path Delay Differences (ps)
Opt level BOOG
LOON 0 1 2 4
0       0        0        0        0 
1       0        0        0        0 
2           +78       -148    +7385 
4   +1432       -29      +283    +7137 

The timings from Alliance synthesis are somewhat artificial and certainly unreachable as they do not include the delay introduced by the wire capacitance. No consideration is given either to the output load, nor to the disadvantages of netlists which have high fanins.

BOOG and LOON can be made to consider all of these effects.

  • setting an input impedance which gives a delay proportional to the input capacitance and which we will consider in the overall netlist performance;
  • setting an output capacitance and including the delay to charge it;
  • adding a wireload capacitance to each cell's input pin capacitance to estimate the real wiring cap, and including this added cap in the critical path delay.

For BOOG synthesis we will not use an input impedance. We will try it for LOON because we want to time the netlist including the input delay. We can review the use of input impedance with LOON synthesis after adding load capacitance, making some library corrections, and adding wireloads and macros.