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We want to set a realistic output load so that BOOG and LOON will choose a netlist capable of driving it effectively. This would mean driving the critical path output either
BOOG will not vary the cell driving the critical path output so that a high drive version can be chosen, nor will it insert buffers or inverters. The netlist synthesised by BOOG is the same independently of the output load.
LOON will choose a higher drive cell to drive a large output load. It will not insert a buffer though. For the multiplier netlist, the critical path output is driven by a 2-XOR gate, and the sclib contains only one of these, an x1 drive strength. So we don't expect the output load to change the synthesised netlist.
We set an output load of 300fF in the LAX file. If the average fanout is 90fF made up of a pin cap of 45fF and a wire cap of 45fF, then the load value chosen of 300fF is a fanout of 300/90 = 3.33.
This is a good value for an output that drives loads in the same physical standard cell area. If the destinations are more distant, for example to other physical blocks, then the wire cap is likely to be bigger and a higher load should be chosen.
We can retime the netlists from the Alliance synthesis by adding a LOON run with opt level 0, a 1.5kΩ input impedance and a 300fF output capacitance.
1 $ OLD_ALLIANCE=/home/cad/alliance-4.0.6 2 $ MBK_TARGET_LIB=$OLD_ALLIANCE/share/cells/sclib 3 $ boog -l loon_0000_000_4 multi8 multi8_o 4 $ loon -l loon_0000_000_2 multi8_o multi8_1 5 $ loon -l loon_1500_300_0 multi8_1 multi8
The results of BOOG synthesis are not affected by the output load. The results of a LOON optimisation do take the load into account as we will see (though not here), so the LAX file we will use for LOON will include the output load.
Since BOOG results are the same with or without a load, we will use 300fF as a load for BOOG synthesis as well in order to be consistent. The input impedance is set to zero.
For LOON synthesis we will either
depending which gives the faster critical path.
Using the original Alliance library and before
the first option is quicker.
Alternatively we can synthesise directly with these conditions.
1 $ boog -l loon_0000_300_2 multi8 multi8_o 2 $ loon -l loon_1500_300_2 multi8_o multi8
The netlists are the same as the previous ones and the critical path delays are all 767ps slower. This is the ramp delay of 2-XOR xr2_y driving 300fF. The gate cannot be made any bigger as it is the largest 2-XOR in the library.
The output resistances of the xr2_y from the xr2_y.vbe VBE file are
ENTITY xr2_y IS GENERIC ( CONSTANT rup_i1_t : NATURAL := 2700; CONSTANT rup_i1_t : NATURAL := 2700; CONSTANT rdown_i1_t : NATURAL := 2340; CONSTANT rdown_i1_t : NATURAL := 2490; CONSTANT rup_i0_t : NATURAL := 2700; CONSTANT rup_i0_t : NATURAL := 2700; CONSTANT rdown_i0_t : NATURAL := 2340; CONSTANT rdown_i0_t : NATURAL := 2490; . .
The average rdown is 2415, and the average of rup
and rdown is 2557.5. The delay driving 300fF is then
2557.5 × 300/1000 = 767.
Note that the two values for rdown is an error. We will deal with this next.