Chapter

Section

The sclib contains some errors in its VBE logic description cells which will be corrected. We will keep the Alliance supplied library in its installation directory, and copy it with modifications to our own private directory which will be used for synthesis. We will also add a simulator delay to all cells except the power supply connectors.

The simulator delay does not affect the synthesis, but makes for a more realistic simulation with ASIMUT.

The changes to make are

  • Removing duplicate lines in the VBE files
  • Correcting the area values
  • Changing the carry cell logic description

Removing duplicate lines in VBE files

When BOOG synthesises a netlist using the supplied sclib, it produces some error and warning messages. The output is shown on the right, and we will fix the source of the messages below:

Generic rup_c_t already exists
Generic rdown_c_t already exists
Generic rup_i1_t already exists
Generic rdown_i1_t already exists
Generic rup_i0_t already exists
Generic rdown_i0_t already exists
Generic rup_i0_f already exists
Generic rdown_i0_f already exists
Generic rup_i1_f already exists
Generic rdown_i1_f already exists

The "generic rup/rdown already exists" messages are caused by duplicate lines in some of the cells' logic description files. These cells are cmx2_y, xr2_y and nxr2_y. The xr2_y for example has

$ egrep 'rup|rdown' xr2_y.vbe | cut -f1 -d-
    CONSTANT rup_i1_t   : NATURAL := 2700;
    CONSTANT rup_i1_t   : NATURAL := 2700;
    CONSTANT rdown_i1_t : NATURAL := 2340;
    CONSTANT rdown_i1_t : NATURAL := 2490;
    CONSTANT rup_i0_t   : NATURAL := 2700;
    CONSTANT rup_i0_t   : NATURAL := 2700;
    CONSTANT rdown_i0_t : NATURAL := 2340;
    CONSTANT rdown_i0_t : NATURAL := 2490  

The rdown duplicates are the values from the two conditions which cause the output to go low. The i0=i1=0 condition gives the value
rdown_i0_t : NATURAL := 2490
and the i0=i1=1 condition gives
rdown_i0_t : NATURAL := 2340.

BOOG and LOON cannot handle this situation. When the same rup or rdown parameter is supplied twice, the synthesis uses the average value. So in the script which copies the Alliance sclib to our private directory, we will comment out one of the duplicates and if the other is different, replace it with the average value.

if [ "$cell" = cmx2_y ]
then
 sed '18 s/^/--/' ${source_dir}/${cell}.vbe  |
 sed '22 s/^/--/' > ${cell}.vbe
elif [ "$cell" = xr2_y ]
then
 sed '17 s/^/--/' ${source_dir}/${cell}.vbe |
 sed '19 s/^/--/' |
 sed '21 s/^\(.*\)\(2490\)\(.*\)$/--&\n\12415\3/' |
 sed '26 s/^/--/' | sed '28 s/^/--/' |
 sed '30 s/^\(.*\)\(2490\)\(.*\)$/--&\n\12415\3/' \
 > ${cell}.vbe
elif [ "$cell" = nxr2_y ]
then
 sed '15 s/^/--/' ${source_dir}/${cell}.vbe |
 sed '17 s/^\(.*\)\(2450\)\(.*\)$/--&\n\12575\3/' |
 sed '22 s/^/--/' | sed '24 s/^/--/' |
 sed '26 s/^\(.*\)\(2450\)\(.*\)$/--&\n\12575\3/' |
 sed '29 s/^/--/' > ${cell}.vbe
else
 cp ${source_dir}/${cell}.vbe .
fi

Wrong area values in VBE files

The area result of 127,015,812 λ2 in the BOOG listing is also strange. The cell height is 42λ; the track pitch is 6λ, so that a three track wide basic gate will be 18λ wide and will have an area of 42×18 = 756λ2. The area given by BOOG is the same as 168,010 gates! A rather large multiplier if true. We will correct the area parameter in the logic description files.

The VBE file for the na2_y 2-input NAND gate has an area parameter of

CONSTANT area : NATURAL := 75600;

which is 100X too big. This is true of all the cells except ndrvp_y, zero_y and the flops. Our copy script modifies area values which are 100X too big by removing the extra two zeros.

sed -i 's/^\( *CONSTANT  *area *: *NATURAL *:= *
[0-9][0-9]*\)\(00\)\( *;.*\)$/\1\3/' ${cell}.vbe

Now BOOG gives an area result of 1,277,388λ2, which is 1,690 gates (divide by 756). If the area values are inconsistent between the cells, then BOOG and LOON are not able to synthesise to area constraints properly.

The corrected library gives completely different BOOG synthesis results. This is caused by the corrected areas of the inverters. In the original Alliance sclib, the largest inverter ndrvp_y has the smallest area, and this inverter is therefore used by BOOG. In the corrected library, the smallest inverter n1_y is used instead.

Logic description changes

sclib cgi2 cell A carry generator cell is an efficient function and we expect it to be chosen. It is chosen by BOOG with opt level 4 but not by the other opt levels. If we change the logic expression, then it is chosen by all opt levels and the resultant netlist is faster.

The carry expression in the original library cell is

f <= not ((si and ci) or (pi and (si or ci)));

We change it to

f <= not ((si or ci) and (pi or (si and ci)));

Although the expressions are equivalent, BOOG is less likely to use a cell with the first one. The second expression also leads to faster netlists.

The corrected library has the same timing, so the results from LOON are generally the same. The wrong area values in the original library, especially the largest inverter which has (wrongly) the smallest area, means that LOON synthesis can give slightly different results when cells are swapped to reduce area.

                  @@@@@@@                             @@@@ @  
                    @@   @@                         @@    @@  
                    @@    @@                       @@      @  
                    @@    @@     @@@       @@@    @@          
                    @@   @@    @@   @@   @@   @@  @@          
                    @@@@@@    @@     @@ @@     @@ @@     @@@@@
                    @@    @@  @@     @@ @@     @@ @@     @ @@ 
                    @@     @@ @@     @@ @@     @@ @@    @  @@ 
                    @@     @@ @@     @@ @@     @@  @@      @@ 
                    @@    @@   @@   @@   @@   @@    @@    @@  
                  @@@@@@@@       @@@       @@@        @@@@    

                         Binding and Optimizing On Gates

             Alliance CAD System 5.0 20060218, boog 5.0 [2003/01/09]
             Copyright (c) 2000-2008,                 ASIM/LIP6/UPMC
             Author(s):                              Francois Donnet
             E-mail        :             alliance-users@asim.lip6.fr

        MBK_VDD        : vdd
        MBK_VSS        : vss
        MBK_IN_LO      : vst
        MBK_OUT_LO     : vst
        MBK_WORK_LIB   : .
        MBK_TARGET_LIB : /home/cad/alliance-4.0.6/share/cells/sclib

Reading parameter file 'boog2.lax'...
50% area - 50% delay optimization
Reading file 'multi8_boom.vbe'...
Controlling file 'boog2.lax'...
Controlling file 'multi8_boom.vbe'...
Reading lib '/home/cad/alliance-4.0.6/share/cells/sclib'...
BEH: f input unused
Mapping Warning: Cell 'zbli_y' isn't supported
Mapping Warning: Cell 'n1_y' isn't supported
Generic rup_c_t already exists
Generic rdown_c_t already exists
Mapping Warning: Cell 'ndrv_y' isn't supported
Mapping Warning: Cell 'mx2p_y' isn't supported
Generic rup_i1_t already exists
Generic rdown_i1_t already exists
Generic rup_i0_t already exists
Generic rdown_i0_t already exists
Mapping Warning: Cell 'np1_y' isn't supported
Generic rup_i0_f already exists
Generic rdown_i0_f already exists
Generic rup_i1_f already exists
Generic rdown_i1_f already exists
Mapping Warning: Cell 'op3_y' isn't supported
Mapping Warning: Cell 'na3p_y' isn't supported
Controlling lib '/home/cad/alliance-4.0.6/share/cells/sclib'...
Preparing file 'multi8_boom.vbe'...
Capacitances on file 'multi8_boom.vbe'...
Unflattening file 'multi8_boom.vbe'...
Mapping file 'multi8_boom.vbe'...
Saving file 'multi8_boog.vst'...
Adding signal 'not_rtlcarry_6 7'
Adding signal 'not_rtlcarry_6 8'
Adding signal 'not_rtlcarry_6 9'
Quick estimated critical path (no warranty)...22988 ps from 'y 1' to 'r 10'
Quick estimated area (with over-cell routing)...127015812 lambda2
Details...
        xr2_y: 346
        no2_y: 316
        ndrvp_y: 47
        nxr2_y: 45
        a2p_y: 27
        noa4_y: 26
        noa3_y: 26
        mx2_y: 26
        na2_y: 21
        no3_y: 11
        a2_y: 4
        noue4_y: 2
        annup_y: 2
        o2_y: 2
        zero_y: 1
        one_y: 1
        Total: 903
Saving critical path in xsch color file 'multi8_boog.xsc'...
End of boog...

Basic sclib 2-NAND gate, 3 tracks wide and 7 tracks tall. The track pitch is 6λ. sclib grid