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Illustration of Metal Percentage Dedicated to Power Supplies
Power straps can run horizontally and vertically in the different metal layers to bring power to the centre of the chip. The most usual convention is to run metal‑1, metal‑3 etc. horizontally, and metal‑2, metal‑4 etc. vertically. This is shown in the drawing on the right.
Here we talk about strap width and strap allocation. The width is the actual width of the straps. The allocation is the space that they occupy, which also includes the spacing to adjacent metal. This spacing can become quite large for wide metal straps.
The usage here is to refer to power strap allocation Apn on metal layer n when referring to all the metal allocated for power supplies; and to supply strap allocation Asn, to mean the metal used for a single power supply. For the usual condition of two power supplies, Vdd and Vss, which have an equal space allocation,
|Asn = Apn ⁄ 2 .|
Similarly we refer to Wpn and Wsn for power strap widths and supply strap widths.
The power supply straps have a certain width and are repeated at a certain pitch. If, as an example for metal-2, they are set to 16µm wide, are spaced 2µm further from other metal than regular wires and repeat every 400µm, then the two supplies together have fraction p of metal-2 allocated to them where
|Ws2 = 16; As2 = Ws2 + 2 + 2; Ap2 = 2 × As2|
|p =||Ap2 ⁄ 400 = 10%||of metal-2 allocated to them.|
This is in addition to the metal‑1 power rails in the standard cells.
Where there are fixed blocks like memory or analog, the lower metal supplies will stop at the block boundary. Whether the higher metal supplies can pass over depends on the block. For analog, generally not. For memories, depending on the design, metal‑5 and higher can pass over.
The presence of the fixed blocks will reduce the core area available for routing on each metal layer n by fraction mn.
I recommend, if not already present in the block, surrounding the block by metal power straps so that the core level power straps can connect easily.