vlsitechnology.org /IR drop /design attributes  
Design Attributes 
IR Drop
Derivations
Certain aspects of the chip specification are listed in the table on the right, along with typical values for a 0.13µm technology. The required power strap width is a function of these parameters.
We derive the variables Ipad, Vcore, G, L and p from these design attributes.
Ipad is the current through each core power supply pad at nominal voltage, taken by dividing the total core current by the number of core Vdd or Vss pads.
Vcore is the voltage at the edge of the core after the drop from the package pin caused by the resistances of the package leadframe, the bond wire and the core supply pad.
G is the conductance of the metal2 plane. Half of the plane is used for Vdd power straps and half for Vss. If less than 100% of the metal2 is used for power, say fraction p, then the conductance will be p⋅G.
L is the parallel metal conductivity coefficient. It shows how much bigger is the total metal conductivity due to multiple metal layers, different metal layer resistivities and strap widths than the conductivity of the metal2 power straps.
Note that normally here k_{w}_{2}=k_{c}_{2}=100%, and if k_{w}_{2}=k_{a}_{2} and the only power straps are in metal2, then L=1.
p is the power strap allocation percentage for metal2. Given the design attributes in the table on the right, we calculate the metal2 power strap allocation and from that the allocation of the other metal power straps.
k_{an} is the relative power strap allocation, the amount of metal layer n allocated to power divided by the amount of metal2 allocated. This is the user deciding how big the straps in each metal layer should be.
k_{wn} is the relative power strap width, the amount of metal layer n used for power divided by the amount of metal2 allocated to power. This is how much of the allocated space can be used for metal, the rest being needed for spacing to adjacent metal.
k_{cn} is the ratio of the conductivity of metal layer n to metal‑2. The metal conductivities (inverse of resistivities) are a feature of the technology and we set k_{c}_{2}=1.
Design Attribute  Typical Value  

Pnom  core power consumption  1W  
ps  fraction of metal1 in the standard cells used for power supplies  22% (for vsclib)  
r_{n}  resistivity of metal layer n in ohms per square  0.07Ω per sq.  
k_{an} 

100%  
k_{wn} 

80%  
m_{n}  percentage of metal layer n which is blocked  30%  
Vdd  the nominal supply voltage  1.2V  
Vddmin  the minimum supply voltage, typically 5% less than the nominal  1.14V  
Vmin  the desired voltage at the centre of the die, typically 10% less than the nominal  1.08V  
Npad  number of core Vdd or core Vss power pads  16  
Rpkg  the resistance of the package leadframe  25mΩ  
Rbond  the resistance of the bond wire  25mΩ  
Rpad  the resistance of the bond pad  100mΩ 
Ipad = 


Vcore = 


G = 


k_{cn} = 


m_{n}′ = 


L = 


p = 
