IR Drop


This web paper presents the principles and methodology for calculating the width of power supply straps in an integrated circuit, given the basic design attributes and an estimate of the core power.

This subject matter is largely ignored in the text books that deal with integrated circuit design. For example, In Weste and Eshraghian Principles of CMOS VLSI Design, chapter 4.6 gives an equation for sizing power conductors in order to avoid problems with electromigration, but does not offer any guidance on sizing them for IR drop, even if admitting that normally this is the more serious problem.

The book by Michael J.S. Smith Application-Specific Integrated Circuits simply talks about electromigration and IR drop (in chapter 17.3.2) without offering any advice on how to size the power buses.

The book CMOS IC Layout Concepts, Methodologies and Tools by Dan Clein has a short chapter, 6.1, on power grids. An example shows vertical metal-2 power straps with (in this paper's terminology) p = 10%, but no explanation about how this number was derived. Just generic talk about how various factors like power consumption, clock rate, average fanout, duty cycle, electromigration and resistance should be used to arrive at the 10% figure.

I hope that this paper fills a gap in the literature, and will prove useful to you. The same subject matter will appear in my upcoming book The Art of Standard Cell Library Design.

Original paper April 25, 2004
Last update October 28, 2007
Graham dot Petley at vlsitechnology dot org