Cadence used to support a small open source standard cell library which could be accessed from crete.cadence.com. It was called the gsclib and it's gone now, but copies might still be around.

My version is 2.0 and was downloaded in January 2004. The basic library is supplied in proprietary Cadence format, but GDS, verilog, VHDL and Synopsys Liberty format files are also supplied.

The cells are drawn in a 0.18µm technology with a track pitch of 0.66µm. The pitch is via to line rather than via to via which would be 0.7µm. The cells are 7.92µm or 12 tracks tall. For the pharosc rules, lambda=0.08µm gives a track spacing of 8¼λ and lambda=0.09µ gives 7 1⁄3λ track spacing and 88λ tall cells..

Preferred routing has metal-2 vertical and metal-3 horizontal. Metal-2 is not used inside the cells. All transistors are aligned vertically and have no bends.

There are 38 cells whose choice was based on the paper by J.L. Noullet and A. Ferreira-Noullet. Only the inverters, buffers and 2-NAND gates have large drive strengths. There is no data sheet, but there is a good doc on the library design philosophy. The basic P transistor size is 2.02µm (22.4λ), and the N is 0.85µm (9.4λ), choices which give symmetrical rise and fall times.

The layout has a number of peculiarities such as not sharing adjacent diffusion (right) which results in large cells. The 2-XOR gate using the pharosc rules would be 70λ (6.3µm) wide and is 7.26µm wide in the gsclib (bottom right). The actual vsclib basic 2-XOR is 64λ wide, and the pharosc rules allow lambda=0.08µm for a typical 0.18µm process, so in this case the 2-XOR width would be 5.12µm.

The layout can't easily be used with most DSM technologies because of closely spaced contacts, incomplete NIMP and PIMP coverage of geometries and even one could say the inconvenient track pitch.

Example of not sharing diffusion areas in DFF layout
Part of DFF layout showing adjacent source/drain regions not sharing diffusion.

2-XOR gate layout (Klayout)
gsclib 2-XOR gate layout