Illinois Institute of Technology (IIT) has developed a standard cell library which has been ported to AMI 0.5µm and 0.35µm, TSMC 0.25µm and TSMC 0.18µm technologies. The library is now known as the Oklahoma State University (OSU) library after its designer Prof. J. Stine moved.

The main library delivery is in proprietary Cadence format, but there are gds layout files and Verilog and VHDL for simulation.

There is a library home page and a download page. The library is quite up to date with the latest release on June 12, 2007.

The cells are 100λ tall with 40λ available for P transistors and 30λ for N ones. The vertical routing pitch (metal-2,‑4 etc) is 8λ and the horizontal pitch is 10λ. The library has been scaled to technologies from 0.5µm to 0.18µm using the following values of lambda:

0.5 0.35 0.25 0.18
0.3µm 0.2µm 0.15µm 0.1µm

This appears to be a simple shrink with no individual layer over or under sizing.

There are limited web data sheets (eg for the TSMC 0.25µm library) which don't show the schematics or the layout. There are 32 cells and only the inverters and buffers have multiple drive strengths.

Many cells use internal metal-2 which will impact routing density. Not all the available space is used for transistors, but still sizes in general are good.

The basic 2-XOR gate (right) is 56λ wide, which compares with 64λ for the vsclib with the pharosc rules. However, the IIT/OSU library needs a large value of lambda, 0.1µm instead of 0.08µm, so the width of the 2-XOR is 5.6µm in IIT and 5.12µm in vsclib.

IIT 2-XOR gate
IIT/OSU standard cell library 2-XOR gate in 0.18µm technology showing lots of metal-2 crossovers.