Synthesis Directory Structure

1. The downloaded sclib is not touched. The directory can also be added to the $MBK_CATA_LIB variable so that the CATAL file used is the original one.
2. The files in the private sclib are copied and edited with a script. The script is mainly concerned with the layout files, but also includes the VBE file corrections and changes to the logic description of the cells.
3. The VBE macros with 0fF and 45fF wireload timing have their own directories.
4. LOON synthesis with 45fF wireloads needs to find all the VBE files in one directory. The 45fF wireload directory contains (i) the 0fF wireload files from the original sclib modified by adding 45fF to the input capacitance; and (ii) the VBE files in sclib100_45_macros copied across. Similarly for 0fF wireload synthesis.
5. BOOG synthesis needs to find all its files in one directory. It uses a directory with min drive strength only cells, except for the inverters. We have eight directories, one for each drive strength inverter and choice of wireload. The VBE files in sclib100_45_min_macros are copied over to the 45fF wireload directories, and similary for the 0fF wireload. BOOG synthesis can be done with the 0fF or 45fF wireload min drive strength libraries. The 0fF gave better results here.
6. The VBE files in the 0fF wireload directory sclib100_0 are copies of the private sclib ones. It is convenient to have a copy so that they can be edited for experimentation.
7. The content of the macro and netlist directories is created by the user.
8. The macro netlists can be accessed by making sure that the MBK_CATA_LIB environment variable, which is the search path for netlists, includes sclib_netlist:

$ echo $MBK_CATA_LIB
MBK_CATA_LIB=.:/home/dev/alliance/vbe/sclib_netlist

A script convert_cell in the private sclib directory edits each sclib cell as it is copied across. The directory contents are made by

1. copying across the contents of the downloaded sclib
2. converting each cell with the convert_cell script

The conversion lists each cell, edits it by prefixing with string convert_cell and then executing it. Then in the 0fF wireload directory we have a script copycells which copies the VBE files from the private sclib and the locally created macros.

In the 45fF wireload directory we have a script makecell which copies a cell from the 0fF wireload directory and adds 45fF to the input pin capacitances. We also have a file copycells which copies across the logic macros and runs makecell for each cell.

The minimum drive strength directory sclib100_45_min_x1 for BOOG contains a script copycells which copies across the cells we want visible to BOOG for its synthesis. The other BOOG directories have similar scripts.