Getting Each Input's Delay

LOON will only buffer an input to reduce its fanin if it is on the critical path. In order to put an input on the critical path, we need to use a LAX file with a higher input impedance on non-critical pins. The extra delay from this higher rin and input capacitance cin will cause the input to be buffered. The question is to which pins we add this higher value of rin and what its value should be.

For each input of the BOOG netlist, we find the critical path delay by synthesising with LOON opt level 0 and a LAX file with rin=50kΩ on the input under test. For the netlist synthesised with BOOG opt level 4 and the x8 library with a 0fF wireload, the delays can be found with a simple script like

1 $ MBK_TARGET_LIB=$ALLIANCE_MOS/vbe/sclib100_0_min_x8
2 $ boog -l loon_0000_300_4 multi8 multi8_o 2>/dev/null >/dev/null
3 $ MBK_TARGET_LIB=$ALLIANCE_MOS/vbe/sclib100_45_min_x8
4 $ for pin in x y
5 $ do
6 $   for bit in 0 1 2 3 4 5 6 7
7 $   do
8 $     sed "/^#I{/,/^}/ s/^\($(echo $pin"("$bit")")\):\(.*\)$/\1:50000;/" loon_1500_300_0.lax > rin.lax
9 $     loon -l rin multi8_o multi8_0 2>/dev/null | grep '^Critical'
10$     grep "^N:${pin} ${bit}" multi8_0.xsc | cut -f4 -d: | cut -f1 -d ' '
11$   done
12$ done

The critical path delay is grepped from the LOON output. The rin×cin delay is grepped from the XSC file written by LOON (see output at right). The Prop delay is the difference and is graphed below, the blue curve for x(0:7) and the red curve for y(0:7).

The dotted line is the maximum delay 27814 which includes the delay contribution of the 1.5kΩ input rin. We have to find the input resistance for each input which will bring its delay up to this maximum value. For pin x(2) it is 1.5kΩ.

This is done with the spreadsheet at the bottom. We could put the resistances in rows 26 and 27 into the LAX file, but I find that this easily causes LOON to crash.

Instead the maximum resistance of 14043Ω is used in the LAX file on any input which has a fanin greater than 4.