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This site contains support material for a book that Graham Petley
is writing, The Art of Standard Cell Library Design.
This material includes standard cell libraries,
which are made available under the terms of the
GNU Lesser General Public Licence.
There are no restrictions on using these libraries in an integrated circuit,
and they can be copied, modified and distributed under terms of your choice
provided that the original copyright is prominently displayed
(see section 6 of the licence).
Standard cell library information
There are five new open source standard cell libraries, the
vsclib,
wsclib,
vxlib,
vgalib and
rgalib.
They have been drawn with the
Graal
software from
Alliance,
part of an extensive open source software suite for designing integrated
circuits with a standard cell design methodology.
The libraries have been characterised in a generic 0.13µm technology.
The spice model comes from the
University of California, Berkeley.
The layout has been drawn using
MOSIS
layer numbers and names and the
pharosc rule set,
and then scaled
to what are slightly oversized 0.13µm rules which should
be compatible with most foundries.
The
vxlib is compatible with the
sxlib
created by the
Alliance software authors. The
vsclib
is a completely new library design. The
wsclib is derived from the
vsclib. The
rgalib and
vgalib
are small gate array type libraries.
The
Alliance
sxlib
has also been characterised in 0.13µm using the same methodology
and converted to the same 0.13µm layout rules.
There is also an
ssxlib which is the
Alliance
sxlib
converted with a script from 1µm to 2µm layout and adjusted to
obey DSM layout rules. The adjustments change the timing slightly.
The characterisation methodology creates a
web data book, and this
is on-line with the cells' layout and schematics.
Recent releases
In Release 8.1, the
wsclib and
ssxlib
have been added. There are variants
called stxlib, vtxlib, vtclib and wtclib
which allow routing on the metal-1 level. See the examples directory in the
release file for more details.
Release 8.2 has increased the size of the
vsclib and
wsclib,
improving a number of the cell layouts and adding a
D flip‑flop.
Two small gate array libraries have also been added.
Release 8.3 has added a latch to the
vsclib and
wsclib,
and expanded the examples directory. Each cell's fixed delay in the
Alliance
VBE
file used for VHDL simulation has been set to the cell delay driving 25fF.
Release 8.4 has some small corrections and
help files for working from a Linux Live CD.
Release 8.5 has much improved support for
Magic
including a single tech file, updated DRC files, completely revised
extraction parameters and extraction flow which avoids the previous
kludge, and
improved colours for viewing the cells.
Library development flow
The library development flow uses
Graal
for the layout entry, and
S2r
to convert the layout to a
CIF file. The
CIF file is read into
Magic
which is used to extract a
Spice deck and write
CIF
and
GDS layout files.
Magic has stronger features than
S2r
for converting layout drawings to
CIF.
The extracted spice decks are simulated with
Winspice3
using a
0.13µm BSIM3
model from the University of California, Berkeley.
A comprehensive characterisation script is used,
making it easy to add new cells.
The transistor schematics for the libraries have been drawn with
Xcircuit,
which uses Postscipt as its native file format.
The characterisation results are formatted with scripts into a
Synopsys Liberty .LIB format and an
Alliance
VBE format.
The
Synopsys format is an industry standard, and the
.LIB
files use table lookup for
accuracy which matches or exceeds that of commercially available libraries. The
Alliance
VBE
format allows the library to be used with the
Alliance
P&R software,
Ocp and
Nero,
and simulated with
Asimut.
OCP
for place and
NERO
for route need their source code
modified and then recompiled to use these libraries. Compiled
versions made under Ubuntu 7.04 on Intel hardware are included in
the examples directory in the library release, and in
http://www.vlsitechnology.org/bin
Help pages
Web pages offer help in downloading, viewing and characterising
the cells.
The Windows help
is for native Windows and for booting a Windows computer from a Linux
Live CD like Ubuntu 6.10 and 7.04. I don't use Windows much so I can't offer
much help on its use with
Alliance. Frankly it is
not an operating system well suited to engineering work,
more like a toy really, so a Linux
Live CD is a good option for Windows users.
The Linux help is for users who
have Linux installed as their operating system.
The libraries were first released on September 25, 2003,
with a number of revisions since then.
There is an extensive
README.txt file to help in using the library.
The text files on this site have all been created on a Linux system
which uses <LF> for new lines. Windows uses <CR><LF>,
and some Windows programs don't properly handle files using <LF> only.
One of these is
Notepad,
the default viewer for TXT files.
Wordpad
allows these files to be viewed properly.
In addition to the standard cell libraries, there is a
discussion of logical effort and how it has
been used for sizing the vsclib and vxlib transistors.
There is a paper on supply line IR drop
(33 pages) and how to size the power supplies to avoid problems.
The paper on
choosing the cells in a standard cell library
shows the benefits of adding cells to a library.
Full details of the revision history are in the
revision.txt file. |
