nd2a standard cell family

2-I/P NAND gate with inverted input
nd2a symbol
Single stage 2-I/P NAND gates with one inverted input. The output P:N ratio is about 2.4 and the stage effort on pin a is 1.2.
z:(a+b') cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vgalib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd2av0x2 2.7  64 3.52 1.32  28.2  5.6f  61  2.27  80  2.04
nd2av0x2
 
Effort
FO4 Log.
a /\
¯_ 1.70
b /\ 1.17 1.22
¯_
nd2av0x2 schematic nd2av0x2 standard cell layout