nd3 standard cell family

3-I/P NAND gate
nd3 symbol
x2 drive strength cell with a P/N ratio of about 3.4.
z:(a*b*c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vgalib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd3v0x2 2.7  64 3.52 1.11  12.3  4.8f  48  2.27  46  2.83
nd3v0x2
 
Effort
FO4 Log.
a /\ 1.55 1.49
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b /\ 1.47 1.49
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c /\ 1.38 1.44
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nd3v0x2 schematic nd3v0x2 standard cell layout