|vlsitechnology.org /vxlib /description|
vxlib standard cell library description
The vxlib is a design rule independent standard cell library which has been drawn with the Alliance Graal editor. The Alliance system allows cells drawn with Graal to be converted to CIF and GDS formats in different technologies by the use of appropriate RDS files. The library release tar file has examples of this layout converted into 0.13µm generic technology.
Note that in the discussion about lambda on this page and elsewhere on this web site, the length of a transistor is 2 lambda, a standard originally set in the classic Mead-Conway book. One advantage of this standard is keeping all widths and spacings on an integer multiple. The vxlib and Alliance sxlib cells instead are drawn with transistor lengths of 1 lambda. Widths and spacings are on a half lambda multiple. There is a 2:1 ratio between the Alliance sxlib rules and regular Mead-Conway lambda rules. When for example, an sxlib cell is described as being 100λ tall, in Graal it will be measured at 50λ tall.
The vxlib is a 100 lambda tall library (which is large) with 7 internal metal tracks on a 10 lambda pitch. The maximum P transistor width is 39 lambda (including available space under the vdd), and the maximum N transistor width is 33 lambda.
The design rule independence is achieved by the use of lambda rules. The rule set used is similar to the one proposed by MOSIS, but is more relaxed and suitable for deep submicron technologies. A comparison of the basic rules is given on the rules page. The cells can be used with others designed to the MOSIS rules, or on their own when typically a more aggressive lambda scaling factor is possible. For generic 0.13µm rules, the SCMOS DEEP rules would need a lambda value of about 0.065µm instead of 0.055µm, and maybe even 0.07µm (the poly overlap of gate at 2.5λ is very short and is the limiting feature; the vxlib rules have a 4λ poly overlap of gate).
In Graal, the basic design rules for wires, contacts and transistors are encoded into the RDS file. If you load a cell into Graal with the wrong RDS file, then the layout is unintelligible. The vxlib can be used with the Alliance supplied cmos.rds file, or one of the vx RDS files: vx100.rds for data entry and viewing with the conventional Alliance lambda rules; vx013.rds for viewing the results of scaling to generic 0.13µm technology and conversion to CIF or GDS files. Other technology files will be provided in the future.
The vxlib rule set is compatible with the vsclib rule set. To convert vxlib Graal layout to generic 0.13µm layout, use lambda=0.11µm; use lambda=0.055µm to convert vsclib layout. The vxlib (and sxlib) also uses some more relaxed design rules, especially the spacing from contact to channel, so the vsclib will not meet strict vxlib/sxlib design rules. The vxlib has some slight rule differences to the Alliance sxlib. This means that slightly different files should be used for converting to real CIF layout. For generic 0.13µm rules, the vxlib uses the vx013.rds file and the sxlib uses the sx013.rds file.
The rule differences are:
The sx013.rds file is supplied for converting the sxlib to 0.13µm. It uses the same value of lambda as the vxlib, but a bigger metal oversize and a diffusion undersize to account for (a) the 2λ metal widths and (b) the 3λ poly overlap of transistor.
The vxlib space allocation is shown in the drawing above right. The nwell height is the same as the sxlib to allow cells from the two libraries to be used together. This is a tall library designed primarily for use in layout with metal-2 running horizontally and metal-3 vertically.
The cells use the same 10 lambda routing pitch as the sxlib, which would give the following routing pitches in different technologies:
|Techno (um)||lambda||routing pitch|
These routing pitches are likely to be significantly larger than the foundry minimum. The advantage of this library is the ease of drawing the layout. The relaxed routing pitch makes it easier to find space for the asymmetric contacts and vias. The library also uses the Alliance convention that the first vertical routing track is a full track inside the cell rather than half a track which represents the smallest design rule. This makes the cells bigger (a basic 2-NAND gate is 100λ×40λ compared for example to 72λ×32λ for the vsclib, 73% bigger), but the extra space makes drawing quite easy and less error prone.
Wherever possible, the cell connectors are designed so that for a single pin they cover two or more horizontal and two or more vertical routing tracks. For any two pins, they cover three or more horizontal and vertical routing tracks; three pins cover four tracks etc. This is shown in the table below for the nr3_x05 cell.
|Number of tracks covered by hor and ver connectors for nr3_x05|
|Single pin (min 2)||Double pin (min 3)||Triple pin (min 4)|
In this example, the cell connections for the pins a,b,c cover only three horizontal tracks, and not four as desired. This reduces flexibility to the P&R software and increases the risk of congestion. If the pins connect to vertical wires, these wires must connect to these three tracks only with no flexibility to connect to an adjacent track.
All transistors in the cells are oriented vertically. Normally the output is positioned at the left of the cell rather than the right because this ensures that the output can be on the first vertical routing grid. The cell architectures are loosely the same as the vsclib.
The basic P/N transistor ratio is set to be 2, except for 3-NAND and 4-NAND gates which use ratios of 2.33 and 2.5. This isn't the fastest ratio, but offers a good compromise between speed and skew and especially simplicity. Some gates have different P/N transistor ratios which favour higher speed at the expense of larger output skews.
The maximum P-transistor size is 39 lambda, the maximum N transistor is 33 lambda, giving a ratio of 1.18 between the area allocated to P and N transistors. This is low and leads to wasted space in many of the cells. A ratio between 1.3 and 1.5 is better when the standard P/N transistor ratio is 2. If the P/N ratio is lower, then a smaller ratio of 1.18 is more suitable.
The naming convention sets a cell's drive strength to be proportional to the effective conductivity of the output P transistor. A single P transistor of 39λ is an x2 drive strength. For each function, either the P or the N transistor area is filled, with the width of the transistors in the other area set by the P:N transistor ratio. Most functions then have a half drive strength function, x05, occupying the same area as the x1, and double drive strengths are made by folding transistors.
This naming convention is the same as the sxlib, although some sxlib cells do not follow the convention, and the sxlib has fewer drive strengths. The naming style follows the sxlib one. The cell names are similar to but different from the sxlib, allowing the 2 libraries to be used together (but if you use the Alliance tools, you will need to put all the cells into the same directory).
|2-AND gate example of vxlib and sxlib compatibility|
|vxlib an2_x2||sxlib a2_x2|
The inverting functions are made from single stage logic. None of the inverting funtions is made from three stage logic. Three stage logic is slow and only ever marginally useful, and has for this reason been excluded from the library.
The gap between successive drive strengths is usually 2:1. A coarse step increases the likelihood that there is a mismatch between the desired gate size and the size actually available from the library. However, for the commonly used gates like inverter and 2-NAND, the step is reduced to something more like 1.5 in order to help get a more optimal timing fit.
vxlib cell architecture.
nr3_x05 layout showing contacts covering two adjacent routing tracks both vertically and horizontally.