|vlsitechnology.org /sxlib /description|
sxlib standard cell library description
The sxlib is a design rule independent standard cell library which has been drawn with the Alliance Graal editor. The Alliance system allows cells drawn with Graal to be converted to CIF and GDS formats in different technologies by the use of appropriate RDS files. The library release tar file has examples of the Alliance sxlib converted into a 0.13µm generic technology. The original layout files are not included. They should be downloaded from the Alliance web site.
Note that in the discussion about lambda on this page and elsewhere on this web site, the length of a transistor is 2 lambda, a standard originally set in the classic Mead-Conway book. One advantage of this standard is keeping all widths and spacings on an integer multiple. The vxlib and Alliance sxlib cells instead are drawn with transistor lengths of 1 lambda. Widths and spacings are on a half lambda multiple. There is a 2:1 ratio between the Alliance sxlib rules and regular Mead-Conway lambda rules. When for example, an sxlib cell is described as being 100λ tall, in Graal it will be measured at 50λ tall.
The sxlib is a 100 lambda tall library (which is large) with 7 internal metal tracks on a 10 lambda pitch. The maximum P transistor width is 40 lambda (including available space under the vdd), and the maximum N transistor width is 34 lambda.
The design rule independence is achieved by the use of lambda rules. The rule set used is similar to the one proposed by MOSIS, but is more relaxed and suitable for deep submicron technologies. A comparison of the basic rules is given on the rules page. The cells can be used with others designed to the MOSIS rules, or on their own when typically a more aggressive lambda scaling factor is possible. For generic 0.13µm rules, the SCMOS DEEP rules would need a lambda value of about 0.065µm instead of 0.055µm, and maybe even 0.07µm (the poly overlap of gate at 2.5λ is very short and is the limiting feature; the sxlib rules have a 3λ poly overlap of gate).
In Graal, the basic design rules for wires, contacts and transistors are encoded into the RDS file. If you load a cell into Graal with the wrong RDS file, then the layout is unintelligible. The sxlib can be used with the Alliance supplied cmos.rds file, or with the sx013.rds for viewing with a 0.13µm rule set, or the sx200.rds for viewing with a nominal 2µm rule set.
The sxlib and vsclib rule sets are compatible. To convert sxlib Graal layout to generic 0.13µm layout, use lambda=0.11µm; use lambda=0.055µm to convert vsclib layout. The sxlib (and vxlib) also uses some more relaxed design rules, especially the spacing from contact to channel, so the vsclib will not meet strict sxlib/vxlib design rules.
The sx013.rds file is supplied for converting the sxlib to 0.13µm. It uses the same value of lambda as the vxlib, but a bigger metal oversize and a diffusion undersize to account for (a) the 2λ metal widths and (b) the 3λ poly overlap of transistor.
The sxlib space allocation is shown in the drawing above right. The nwell height is the same as the vxlib, allowing cells from the two libraries to be used together. This is a tall library designed primarily for use in layout with metal-2 running horizontally and metal-3 vertically.
The cells use a 10 lambda routing pitch, which would give the following routing pitches in different technologies:
|Techno (um)||lambda||routing pitch|
These routing pitches are likely to be significantly larger than the foundry minimum. The advantage of this library is the ease of drawing the layout. The library has its first vertical routing track a full track inside the cell rather than half a track which represents the smallest design rule. This makes the cells bigger (a basic 2-NAND gate is 100x40 lambda compared for example to 72x32 lambda for the vsclib) but the extra space makes drawing quite easy and less error prone.
All transistors in the cells are oriented vertically. Metal-1 connected to inputs and outputs is made as tall as possible in order to ease the routing problem. Horizontal connections are made in Metal-2.
The basic P/N transistor ratio is set to be about 2 for most cells, so that output drive characteristics are consistent across the library.
The maximum P-transistor size is 40 lambda, the maximum N transistor is 34 lambda, giving a ratio of 1.18 between the area allocated to P and N transistors.
The naming convention sets a cell's drive strength to be proportional to the effective width of the output P transistor for most cells. The exceptions are the x2 and x4 inverters and the x1 3-NOR and 4-NOR gates. A single P transistor of 40λ is an x2 drive strength. An x1 drive strength is either a single P transistor 20&lambda wide or 2 series 40λ P transistors.
The high drive version of the inverting functions (except the inverters) is a 3-stage logic, which is slow. The low and high drive versions of the non-inverting functions use the same input stage, so input pin capacitances are equal.
The sxlib can be used with the vxlib, but if you use the Alliance tools, you will need to put all the cells into the same directory.
sxlib cell architecture.