vlsitechnology.org /software versions | |
Software and versions used |
Tool | Version | Function |
---|---|---|
Graal | 5.0 20060509 |
Lambda based layout editor. Used to capture the layout of all the cells |
Magic | 7.5.95 | Lambda based layout editor. Layout imported thru CIF interface. Used to write out spice decks and production worthy CIF and GDS files. Layout uses pharosc.tech to describe technology and which uses features not supported in versions earlier than 7.5. |
Xcircuit | 3.4.26 with TCL |
Schematic editor based on postcript. Used to create schematics of all the cells. The schematics don't work with some other versions of Xcircuit. |
Winspice | 1.05.07 | Spice simulator. Used to simulate the cells and write output files which are then elaborated by a characterisation scipt. Version 1.05.08 doesn't support the spice models in the free version, and runs more slowly. |
S2r | 5.0 20060509 |
Program to convert AP files from Graal to CIF and GDS files. Used here to produce a CIF file for import into Magic. |
Flatrds | 5.0 20060509 |
Utility which can convert CIF to GDS and vice versa. Used to make GDS when the ascii CIF files have been manually hacked. |
Dreal | 5.0 20060509 |
Simple layout editor which uses CIF or GDS files. Used to visualise CIF or GDS files and make bitmap plots. |
Druc | 5.0 20060509 |
DRC rule checker. Checks AP files (from Graal) using rules expressed in microns. |
Lvx | 5.0 20060509 |
Layout versus schematic checker. Will check two structural VHDL descriptions for equivalence. |
Ocp | 5.0 20060218 |
Placement program for standard cells. Alliance supplied version will only place cells compatible with the sxlib, like the vxlib. In order to use the program with the vsclib, wsclib, rgalib and vgalib, the source files must be hacked as described in the Alliance archives. Compiled copies of the different ocp versions have been included in the examples directory. Note that the latest release, 20060509 doesn't work properly. |
Nero | 5.0 20060509 |
Routing program for standard cells. Alliance supplied version will only route cells compatible with the sxlib, like the vxlib. In order to use the program with the other libraries, the source files must be hacked as described in the Alliance archives Compiled copies of the different ocp versions have been included in the examples directory. |
Boog | 5.0 20060218 |
Simple synthesis tool for converting RTL VHDL description to structural VHDL. Used in the example for the VHDL to layout flow. |
Loon | 5.0 20060509 |
Program which will optimise a structural VHDL netlist. |
Xsch | 5.0 20060509 |
Program which will visualise a VHDL description as a schematic and show its critical path if the associated xsc file is present. |
Liberty_parse | 2.4 | Analyses a .LIB file and reports syntax errors. A user name and password is required before downloading the program. |
Libscr | 7.5 | Screens a .LIB file and reports inconsistencies. A user name and password is required before downloading the program. |