Information about the standard cell library download

Seven standard cell libraries are provided. The cells' layout has been drawn in Graal and then converted to CIF and GDS format in 0.13µm technology. Graal is a portable layout editor, which means that layout is drawn in a nominal 1µm or 2µm technology and is then scaled to the desired technology (0.13µm in our case) by an appropriate rule file.

The sxlib and vxlib have been drawn in Graal with a transistor channel length of 1µm and the other libraries have been drawn with 2µm transistors. 2µm technology matches the Mead-Conway and MOSIS conventions and has the advantage of avoiding fractional layout rules.

1µm technology is the Alliance choice with the sxlib, and the vxlib has been drawn to match. The ssxlib is the sxlib converted to 2µm layout rules. The vxlib has been converted to 2µm layout (the vsxlib), which has the same electrical characteristics as the 1µm layout.

The term lambda is used to describe the nominal layout design rules. For Mead-Conway and MOSIS 1 lambda is half the transistor channel length. For Alliance 1 lambda equals the transistor channel length. On this site the Mead-Conway convention has been used, which means that if the sxlib is described as being 100λ tall, it has been drawn with a height of 50λ in Graal using the Alliance lambda definition.

A brief description of the 7 libraries.

• The sxlib is a 100λ tall library provided by the Alliance software developers with 61 of the cells characterised here. The layout design rule set used has some violations with the vsclib rule set.
• The ssxlib is the same 100λ tall library with the source layout modified to make it compatible with the vsclib lambda layout rules.
• The vxlib is a 100λ tall library compatible with the sxlib with currently 96 cells. The layout rule set is compliant with the vsclib rules, with some rules being larger.
• The vsclib is a 72λ tall library with currently 320 cells.
• The wsclib is an 80λ tall library with currently 320 cells. The vsclib and wsclib use the vsclib layout rule set and their layout is identical except for substrate and well contacts.
• The vgalib is a minimum set 88λ tall gate array library using the vsclib rules with currently 20 cells. The base cell is a conventional 4 transistor cell.
• The rgalib is a minimum set 88λ tall gate array library using the vsclib rules with currently 23 cells. The 4 transistor base cell connects the P and N transistors in poly which limits the possible P:N transistor ratios.

All 7 libraries have layout drawn with Graal, schematics drawn with Xcircuit, cells extracted with Magic and characterised with Winspice, and have a web data book.

The software and versions used for the library are listed here.