UP PREV NEXT

Alliance Synthesis, BOOM and BOOG

The Alliance design flow is a complete one from VHDL description, through synthesis to P&R, verification and simulation. The part we are interested in here is the synthesis steps which use the programs BOOM, BOOG and LOON, and the simulator ASIMUT which is used to check that the function of each netlist is identical.

BOOM reads a VHDL behavioural description and writes an equivalent optimised VHDL boolean network. The output can be different for each BOOM run, so for the work here BOOM is run once and the output file used as the starting point for all further synthesis.

BOOG maps a behavioural description, like the one produced by BOOM, onto a standard cell library. The boolean functions present in the input file are matched to the functions in the standard cell library. The cell library is a collection of VBE files in one directory pointed to by the environment variable MBK_TARGET_LIB. The Alliance tools are controlled by a number of these environment variables. As an example, on my system they are:

MBK_CATAL_NAME=CATAL
MBK_CATA_LIB=/home/dev/alliance/cells/vsclib
MBK_IN_LO=vst
MBK_IN_PH=ap
MBK_OUT_LO=vst
MBK_OUT_PH=ap
MBK_SCALE_X=1000
MBK_SPI_MODEL=/home/dev/alliance/etc/spimodel.cfg
MBK_SPI_NAMEDNODES=1
MBK_SPI_NETNAME=N
MBK_TARGET_LIB=/home/dev/alliance/cells/vsclib
MBK_VDD=vdd
MBK_VSS=vss
MBK_WORK_LIB=.

The cell library VBE files describe the function, timing and area information, as shown below in a basic 2-NAND for the vsclib and 0.13um technology.

ENTITY nd2v0x2 IS
GENERIC (
  CONSTANT area          : NATURAL := 2304;
  CONSTANT cin_a         : NATURAL := 5;
  CONSTANT cin_b         : NATURAL := 6;
  CONSTANT rdown_a_z     : NATURAL := 1840;
  CONSTANT rdown_b_z     : NATURAL := 1840;
  CONSTANT rup_a_z       : NATURAL := 2460;
  CONSTANT rup_b_z       : NATURAL := 2470;
  CONSTANT tphl_a_z      : NATURAL := 32;
  CONSTANT tphl_b_z      : NATURAL := 34;
  CONSTANT tplh_b_z      : NATURAL := 44;
  CONSTANT tplh_a_z      : NATURAL := 50;
  CONSTANT transistors   : NATURAL := 4
);
PORT (
  a      : in  BIT;
  b      : in  BIT;
  z      : out BIT;
  vdd    : in  BIT;
  vss    : in  BIT
);
END nd2v0x2;

ARCHITECTURE behaviour_data_flow OF nd2v0x2 IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
  REPORT "power supply is missing on nd2v0x2"
  SEVERITY WARNING;
  z <= not (a and b) after 900 ps;
END;

The timing model used by Alliance is a simple Prop-Ramp model. This means that each cell has an intrinsic delay (the Prop) and an output driving resistance (the Ramp). Each cell's delay is then the sum of Prop + Ramp × Load. Furthermore, the delay considered during synthesis optimisation is the average of the rise and fall delays, so circuits which depend on prefential rise or fall delays cannot be properly synthesised by Alliance.

BOOG considers timing in a limited manner.

In order to exercise some user control over this process, a dedicated BOOG library has been created which uses an idealised Logical Effort type of timing. The cells' Prop delays have been adjusted to try to favour faster netlists. The 2-AND and 2-NOR gate BOOG VBE files are listed below as an example.

ENTITY an2v0x05 IS                               ENTITY nr2v1x05 IS
GENERIC (                                        GENERIC (
  CONSTANT area          : NATURAL := 2880;        CONSTANT area          : NATURAL := 2304;
  CONSTANT cin_b         : NATURAL := 4;           CONSTANT cin_a         : NATURAL := 5;
  CONSTANT cin_a         : NATURAL := 4;           CONSTANT cin_b         : NATURAL := 5;
  CONSTANT rdown_b_z     : NATURAL := 5000;        CONSTANT rdown_a_z     : NATURAL := 5000;
  CONSTANT rdown_a_z     : NATURAL := 5000;        CONSTANT rdown_b_z     : NATURAL := 5000;
  CONSTANT rup_b_z       : NATURAL := 5000;        CONSTANT rup_a_z       : NATURAL := 5000;
  CONSTANT rup_a_z       : NATURAL := 5000;        CONSTANT rup_b_z       : NATURAL := 5000;
  CONSTANT tphh_a_z      : NATURAL := 400;         CONSTANT tplh_a_z      : NATURAL := 50;
  CONSTANT tphh_b_z      : NATURAL := 400;         CONSTANT tplh_b_z      : NATURAL := 50;
  CONSTANT tpll_b_z      : NATURAL := 400;         CONSTANT tphl_b_z      : NATURAL := 50;
  CONSTANT tpll_a_z      : NATURAL := 400;         CONSTANT tphl_a_z      : NATURAL := 50;
  CONSTANT transistors   : NATURAL := 6            CONSTANT transistors   : NATURAL := 4
);                                               );
PORT (                                           PORT (
  a      : in  BIT;                                 a  : in  BIT;
  b      : in  BIT;                                 b  : in  BIT;
  z      : out BIT;                                 z  : out BIT;
  vdd    : in  BIT;                                 vdd        : in  BIT;
  vss    : in  BIT                                  vss         : in  BIT
);                                                );
END an2v0x05;                                     END nr2v1x05;

ARCHITECTURE behaviour_data_flow OF an2v0x05 IS   ARCHITECTURE behaviour_data_flow OF nr2v1x05 IS

BEGIN                                             BEGIN
  ASSERT ((vdd and not (vss)) = '1')                ASSERT ((vdd and not (vss)) = '1')
  REPORT "power supply is missing on an2v0x05"      REPORT "power supply is missing on nr2v1x05"
  SEVERITY WARNING;                                 SEVERITY WARNING;
  z <= (b and a) after 1000 ps;                     z <= not (a or b) after 900 ps;
END;                                              END;

The non-inverting Prop delay of the AND gate is made much larger than the inverting Prop delay of the NOR gate. If it is smaller, say 100 instead of 400, then BOOG will construct a slower netlist that uses 2-AND gates instead of 2-NOR gates. This is also what happens when BOOG uses the vsclib 0.13um VBE files.

A limitation of the Alliance synthesis is the ability to use only cells with one output.

UP PREV NEXT