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The multiplier is one supplied with the Alliance tool set. It performs a multiply on 2 8-bit inputs and gives a 16-bit result. The standard cell library is the vsclib characterised with a generic 0.13um Spice deck from the University of California, Berkeley using Winspice.
The general requirements put on the multiplier synthesis are
The multiplier timing is measured including any input pin capacitance delay. The input delay is measured as an RC delay where the R delay is set to 1kΩ (=1ns/pF or 1ps/fF). For the 0.13um technology and library chosen, this corresponds roughly to an x3 drive strength. On this basis, an input pin with a capacitance of 214fF will have a delay of 214ps.
The multiplier timing will include 6fF of estimated wire capacitance (called a 6fF wireload). This is a reasonable estimate for a 0.13um technology. If no allowance is made for interconnect, then the actual multiplier performance will definitely be slower and the gates will also be underbuffered. Using a sensible wireload is the right way to size the gates properly. The timing also includes the delay of the output driving a 50fF load.
The timing is measured in this way in order to make sure that delays belonging to the multiplier are not pushed outside, either by large input capacitances or by ignoring realistic interconnect capacitances.