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Multiplier Example for Standard Cell Selection

This experiment measures the performance of an 8×8 multiplier synthesised with different sets of cells from a standard cell library. The objective is to determine which set of cells gives the best performance.

8-bit multiplier The multiplier is one supplied with the Alliance tool set. It performs a multiply on 2 8-bit inputs and gives a 16-bit result. The standard cell library is the vsclib characterised with a generic 0.13um Spice deck from the University of California, Berkeley using Winspice.

The general requirements put on the multiplier synthesis are

  1. The inputs should not have a high fanin or input capacitance. Transferring the timing problems outside the IP block, for example because the input pin capacitance is very high, is not a good design practice.
  2. The output drive strength should be x2 or bigger. Even if an output is not on a critical path, it is is undesirable if a large post-layout load slows the output excessively. This is avoided by defining a minimum output drive strength.
  3. The design objective is a multiplier with minimum delay.
  4. Allowance should be made for interconnect capacitance. An estimated value of 6fF will be used for each destination pin.
  5. A freely available synthesis software will be used. The tool set from Alliance has been chosen.

input resistance The multiplier timing is measured including any input pin capacitance delay. The input delay is measured as an RC delay where the R delay is set to 1kΩ (=1ns/pF or 1ps/fF). For the 0.13um technology and library chosen, this corresponds roughly to an x3 drive strength. On this basis, an input pin with a capacitance of 214fF will have a delay of 214ps.

The multiplier timing will include 6fF of estimated wire capacitance (called a 6fF wireload). This is a reasonable estimate for a 0.13um technology. If no allowance is made for interconnect, then the actual multiplier performance will definitely be slower and the gates will also be underbuffered. Using a sensible wireload is the right way to size the gates properly. The timing also includes the delay of the output driving a 50fF load.

The timing is measured in this way in order to make sure that delays belonging to the multiplier are not pushed outside, either by large input capacitances or by ignoring realistic interconnect capacitances.