Alliance Synthesis LOON

LOON reads a structural VHDL netlist and optimises it by selecting the best cell in the library for each instance. Best means the one giving the fastest critical path and the smallest area. When BOOG has been used to create the initial structural VHDL netlist, this optimisation is essential since BOOG only uses one drive strength for each logical function.

The LOON synthesis can be controlled by a LAX file. This is used to set the input resistance, the output capacitive load and the synthesis priority level, as shown below.

The M{4} line sets the priority at 4, which means 100% delay and 0% area optimisation. A priority of 0 means 100% area and 0% delay optimisation, priority 1 is 75% area and 25% delay and so forth. Priority levels 2-4 will insert buffers if these improve the critical path, while priority levels 0-1 never will. In practice, priority levels 2 and 3 give the same results, and if no buffers are inserted, the result is the same as priority level 1. Priority level 4 does not always give the fastest critical path. Generally priority level 0 gives the smallest result and level 4 gives the largest.

The lines after #I{ set an input resistance in ohms. This is used to calculate the input delay along with the input pin capacitance coming from the values in the library VBE files. This input delay is part of the critical path and is used by LOON in its optimisation.

The lines after #C{ set the output load in femtofarads. The critical path delay includes the delay of the output gate driving this load.

LOON measures the critical path using the average of the rise and fall delays for each gate.

Excerpt from a critical path The xor2v0x2 gate has a fanout of one driving pin c of the xor3v1x2. The capacitance of pin c is 13fF.
The average drive strength of the xor2v0x2 is

(1.32+1.75)÷2 = 1.535.

The Ramp delay is then 1.535×13 = 20ps.
The average xor2v0x2 Prop delay is

(35+80+61+86)÷4 = 65ps.

The average xor2v0x2 delay is then

Prop+Ramp = 65+20 = 85ps.

Note that the drive strengths of the xor2v0x2 gate are already averaged, since the drive strength is typically different if the XOR is inverting or non-inverting. But with the simplified Alliance timing model, this difference cannot be modelled and an average value is used.

 xor2v0x2      1  b->z      85
 xor3v1x2      1  c->z      79
Excerpt from xor2v0x2.vbe
ENTITY xor2v0x2 IS
  CONSTANT rdown_b_z     : NATURAL := 1320;
  CONSTANT rup_b_z       : NATURAL := 1750;
  CONSTANT tphl_b_z      : NATURAL := 35;
  CONSTANT tplh_b_z      : NATURAL := 80;
  CONSTANT tphh_b_z      : NATURAL := 61;
  CONSTANT tpll_b_z      : NATURAL := 86;
  z <= (b xor a) after 1000 ps;
Excerpt from xor3v1x2.vbe
ENTITY xor3v1x2 IS
  CONSTANT cin_c         : NATURAL := 13;
  z <= ((a xor b) xor c) after 1000 ps;

or4 netlist LOON will only change the drive strength of gates that are on the critical path. If, as a result of sizing up a gate, the critical path changes, then LOON will consider the new critical path.
LOON will not:

The last three of these limitations are in fact requirements set for the multiplier synthesis. The outputs should all be buffered up to x2 drive strength or more, regardless of whether they are on a critical path. All inputs should be buffered to keep down their input capacitance. The timing optimisation should use 6fF of estimated wire capacitance per fanout.

The limitations can be overcome by using scripts and special synthesis flows.

 $ MBK_TARGET_LIB=../vsclib013_0
 $ loon -x 0 -l loon4 multi8 multi8_0
 $ MBK_TARGET_LIB=../vsclib013_6
 $ loon -x 0 -l loon1 multi8_0 multi8
 $ MBK_TARGET_LIB=../vsclib013_0
 $ loon -x 0 -l loon0 multi8 multi8_0
 $ MBK_TARGET_LIB=../vsclib013_6
 $ loon -x 0 -l loon4 multi8_0 multi8
A LOON synthesis script is a sequence of LOON commands alternately using the 0fF and 6fF wireload libraries, and using whichever priority seems to give the best results. This sequence is continued until the critical path reaches its minimum value.