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The LOON synthesis can be controlled by a LAX file. This is used to set the input resistance, the output capacitive load and the synthesis priority level, as shown below.
#M{4} #I{ x(0):1000; ... x(7):1000; y(0):1000; ... y(7):1000; } #C{ r(15):50; ... r(0):50; } 
The M{4} line sets the priority at 4, which means
100% delay and 0% area optimisation. A priority of 0 means
100% area and 0% delay optimisation, priority 1 is 75% area
and 25% delay and so forth. Priority levels 24 will insert
buffers if these improve the critical path, while priority
levels 01 never will. In practice, priority levels 2 and 3
give the same results, and if no buffers are inserted, the
result is the same as priority level 1. Priority level 4
does not always give the fastest critical path. Generally
priority level 0 gives the smallest result and level 4 gives
the largest.
The lines after #I{ set an input resistance in ohms. This is used to calculate the input delay along with the input pin capacitance coming from the values in the library VBE files. This input delay is part of the critical path and is used by LOON in its optimisation. The lines after #C{ set the output load in femtofarads. The critical path delay includes the delay of the output gate driving this load. 
LOON measures the critical path using the average of the rise and fall delays for each gate.
Excerpt from a critical path 
The xor2v0x2 gate has a fanout of one driving pin
c of the xor3v1x2.
The capacitance of pin c is 13fF. The average drive strength of the xor2v0x2 is (1.32+1.75)÷2 = 1.535. The Ramp delay is then 1.535×13 = 20ps. The average xor2v0x2 Prop delay is (35+80+61+86)÷4 = 65ps. The average xor2v0x2 delay is then Prop+Ramp = 65+20 = 85ps. Note that the drive strengths of the xor2v0x2 gate are already averaged, since the drive strength is typically different if the XOR is inverting or noninverting. But with the simplified Alliance timing model, this difference cannot be modelled and an average value is used. 
xor2v0x2 1 b>z 85 xor3v1x2 1 c>z 79  
Excerpt from xor2v0x2.vbe  
ENTITY xor2v0x2 IS GENERIC ( ... CONSTANT rdown_b_z : NATURAL := 1320; CONSTANT rup_b_z : NATURAL := 1750; CONSTANT tphl_b_z : NATURAL := 35; CONSTANT tplh_b_z : NATURAL := 80; CONSTANT tphh_b_z : NATURAL := 61; CONSTANT tpll_b_z : NATURAL := 86; ... z <= (b xor a) after 1000 ps; END;  
Excerpt from xor3v1x2.vbe  
ENTITY xor3v1x2 IS GENERIC ( ... CONSTANT cin_c : NATURAL := 13; ... z <= ((a xor b) xor c) after 1000 ps; END; 
LOON will only change the drive strength of gates that
are on the critical path. If, as a result of sizing up a gate,
the critical path changes, then LOON will consider the new
critical path.
LOON will not:
The last three of these limitations are in fact requirements set for the multiplier synthesis. The outputs should all be buffered up to x2 drive strength or more, regardless of whether they are on a critical path. All inputs should be buffered to keep down their input capacitance. The timing optimisation should use 6fF of estimated wire capacitance per fanout.
The limitations can be overcome by using scripts and special synthesis flows.
for bit in 7 6 5 4 3 2 1 0 do for operand in x y do ./make_lax multi8 "${operand}(${bit})" 80 15000 30 loon4xy 2 0 loon x 0 l loon4xy multi8 multi8_0 x2y vst vst multi8_0 multi8 done done 
 0Ff wireload  6fF wireload ENTITY cgi2v0x1 IS ENTITY cgi2v0x1 IS GENERIC ( GENERIC ( ... ... CONSTANT cin_a : NATURAL := 8; CONSTANT cin_a : NATURAL := 14; CONSTANT cin_b : NATURAL := 9; CONSTANT cin_b : NATURAL := 15; CONSTANT cin_c : NATURAL := 5; CONSTANT cin_c : NATURAL := 11; ... ... END; END; 
ENTITY or4v0x2 IS ENTITY or4v5x2 IS GENERIC ( GENERIC ( CONSTANT area : NATURAL := 6336; CONSTANT area : NATURAL := 9216; CONSTANT cin_a : NATURAL := 14; CONSTANT cin_c : NATURAL := 14; CONSTANT cin_b : NATURAL := 14; CONSTANT cin_a : NATURAL := 15; CONSTANT cin_c : NATURAL := 13; CONSTANT cin_b : NATURAL := 15; CONSTANT cin_d : NATURAL := 13; CONSTANT cin_d : NATURAL := 10; CONSTANT rdown_a_z : NATURAL := 1700; CONSTANT rdown_a_z : NATURAL := 1940; CONSTANT rdown_b_z : NATURAL := 1700; CONSTANT rdown_b_z : NATURAL := 1940; CONSTANT rdown_c_z : NATURAL := 1700; CONSTANT rdown_c_z : NATURAL := 1940; CONSTANT rdown_d_z : NATURAL := 1700; CONSTANT rdown_d_z : NATURAL := 1940; CONSTANT rup_a_z : NATURAL := 2150; CONSTANT rup_a_z : NATURAL := 2470; CONSTANT rup_b_z : NATURAL := 2140; CONSTANT rup_b_z : NATURAL := 2470; CONSTANT rup_c_z : NATURAL := 2120; CONSTANT rup_c_z : NATURAL := 2470; CONSTANT rup_d_z : NATURAL := 2120; CONSTANT rup_d_z : NATURAL := 2470; CONSTANT tpll_a_z : NATURAL := 188; CONSTANT tphh_a_z : NATURAL := 155; CONSTANT tphh_b_z : NATURAL := 147; CONSTANT tphh_b_z : NATURAL := 147; CONSTANT tphh_c_z : NATURAL := 128; CONSTANT tphh_c_z : NATURAL := 130; CONSTANT tphh_d_z : NATURAL := 102; CONSTANT tphh_d_z : NATURAL := 79; CONSTANT tphh_a_z : NATURAL := 161; CONSTANT tpll_a_z : NATURAL := 141; CONSTANT tpll_b_z : NATURAL := 177; CONSTANT tpll_b_z : NATURAL := 130; CONSTANT tpll_c_z : NATURAL := 156; CONSTANT tpll_c_z : NATURAL := 109; CONSTANT tpll_d_z : NATURAL := 121; CONSTANT tpll_d_z : NATURAL := 84; CONSTANT transistors : NATURAL := 14 CONSTANT transistors : NATURAL := 15 ); ); PORT ( PORT ( a : in BIT; a : in BIT; b : in BIT; b : in BIT; c : in BIT; c : in BIT; d : in BIT; d : in BIT; z : out BIT; z : out BIT; vdd : in BIT; vdd : in BIT; vss : in BIT vss : in BIT ); ); END or4v0x2; END or4v5x2; ARCHITECTURE behaviour_data_flow OF or4v0x2 IS ARCHITECTURE behaviour_data_flow OF or4v5x2 IS BEGIN BEGIN ASSERT ((vdd and not (vss)) = '1') ASSERT ((vdd and not (vss)) = '1') REPORT "power supply is missing on or4v0x2" REPORT "power supply is missing on or4v5x2" SEVERITY WARNING; SEVERITY WARNING; z <= (((a or b) or c) or d) after 1200 ps; z <= (((a or b) or c) or d) after 1200 ps; END; END; 

A LOON synthesis script is a sequence of LOON commands alternately using the 0fF and 6fF wireload libraries, and using whichever priority seems to give the best results. This sequence is continued until the critical path reaches its minimum value. 
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