xnr2 standard cell family

2-I/P exclusive NOR gate
xnr2 symbol
4 XNOR gates designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:(a^b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xnr2v0x05 2.7  64 3.52  0.62  12.9  2.3f  84  6.44  86  5.61
xnr2v8x05 3.0  72 3.96  0.83  23.7  2.3f 129  5.00 139  4.04
xnr2v0x1 3.0  72 3.96  0.98  18.9  3.3f  81  4.21  84  3.74
xnr2v6x1 3.0  72 3.96 1.29  20.5  6.0f  79  4.30  75  3.09
xnr2v0x2 4.3 104 5.72 1.96  32.9  6.9f  68  2.05  74  1.78
xnr2v0x3 5.7 136 7.48 2.91  50.3  9.9f  69  1.37  75  1.21
xnr2v0x4 7.0 168 9.24 3.90  65.6 12.9f  69  1.03  74  0.90
xnr2v0x05
 
Effort
FO4 Log.
a /\ 1.74 1.46
¯_ 2.27
b /\ 2.05 2.52
¯_ 2.13
xnr2v0x05 schematic xnr2v0x05 standard cell layout
xnr2v8x05
 
Effort
FO4 Log.
a /\ 2.68 1.24
¯_ 2.37
b /\ 2.53 1.96
¯_ 2.52
xnr2v8x05 schematic xnr2v8x05 standard cell layout
xnr2v0x1
 
Effort
FO4 Log.
a /\ 1.70 1.42
¯_ 2.19
b /\ 1.97 2.43
¯_ 2.02
xnr2v0x1 schematic xnr2v0x1 standard cell layout
xnr2v6x1
 
Effort
FO4 Log.
a /\ 2.13 2.76
¯_ 2.61
b /\ 1.90 2.77
¯_ 2.76
xnr2v6x1 schematic xnr2v6x1 standard cell layout
xnr2v0x2
 
Effort
FO4 Log.
a /\ 1.56 1.41
¯_ 2.01
b /\ 1.93 2.26
¯_ 2.05
xnr2v0x2 schematic xnr2v0x2 standard cell layout
xnr2v0x3
 
Effort
FO4 Log.
a /\ 1.56 1.37
¯_ 2.00
b /\ 1.90 2.24
¯_ 2.04
xnr2v0x3 schematic xnr2v0x3 standard cell layout
xnr2v0x4
 
Effort
FO4 Log.
a /\ 1.52 1.34
¯_ 1.97
b /\ 1.92 2.24
¯_ 2.04
xnr2v0x4 schematic xnr2v0x4 standard cell layout