xnai21 standard cell family

2-XNOR into 2-NAND
xnai21 symbol
Minimum size 2-XNOR gates followed by a 2-NAND, implemented as a single gate with a single stage inverting delay and a 2-stage non-inverting delay. The NAND gate is made by adding a series N-transistor in the pull down path and a parallel P-transistor to the pull up path. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:((a1^a2)'*b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xnai21v0x05 3.3  80 4.40  0.94  21.1  5.3f  79  4.42  65  3.44
xnai21v1x05 3.3  80 4.40  0.91  21.0  5.2f  79  4.42  65  3.44
xnai21v2x05 3.0  72 3.96  0.98  20.6  5.5f  75  4.43  62  3.43
xnai21v0x05
 
Effort
FO4 Log.
a1 /\ 1.78 1.58
¯_ 2.47
a2 /\ 2.26 2.75
¯_ 2.19
b /\ 1.84 1.57
¯_
xnai21v0x05 schematic xnai21v0x05 standard cell layout
xnai21v1x05
 
Effort
FO4 Log.
a1 /\ 1.78 1.59
¯_ 2.47
a2 /\ 2.25 2.73
¯_ 2.18
b /\ 1.83 1.57
¯_
xnai21v1x05 schematic xnai21v1x05 standard cell layout
xnai21v2x05
 
Effort
FO4 Log.
a1 /\ 1.78 1.59
¯_ 2.49
a2 /\ 2.28 2.84
¯_ 2.16
b /\ 1.75 1.45
¯_
xnai21v2x05 schematic xnai21v2x05 standard cell layout