xnr3 standard cell family

3-I/P exclusive NOR gate
xnr3 symbol
The cells are made from a 2-XNOR gate and a 2-XOR gate. The a and b inputs are xnored and input to a 2-XOR gate with input c. Inputs a and b have 2 to 4 stage delays, and input c has 1 or 2 stage delays. The xnr3v1x05 is made from an xnr2v0x05 and xor2v0x05; the xnr3v1x1 from an xnr2v0x1 and xor2v0x1; the xnr3v1x2 from an xnr2v0x1 and xor2v0x2.
This configuration is faster and smaller than making the function with 3 series P and N transistors driving the output. The delay shown is from pin b, while pin c is the fastest input.
z:(a^b^c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xnr3v1x05 5.3 128 7.04 1.48  36.6  5.1f 150  6.17 149  4.75
xnr3v1x1 5.3 128 7.04 2.29  56.8  7.1f 150  3.52 149  2.58
xnr3v1x2 7.7 184 10.12 3.35  86.2  7.0f 166  1.82 167  1.34
xnr3v1x05
 
Effort
FO4 Log.
a /\ 3.42 2.19
¯_ 3.42
b /\ 3.74 3.26
¯_ 3.74
c /\ 2.09 2.49
¯_ 2.14
xnr3v1x05 schematic xnr3v1x05 standard cell layout
xnr3v1x1
 
Effort
FO4 Log.
a /\ 3.12 1.69
¯_ 3.13
b /\ 3.38 2.51
¯_ 3.37
c /\ 1.93 2.29
¯_ 1.93
xnr3v1x1 schematic xnr3v1x1 standard cell layout
xnr3v1x2
 
Effort
FO4 Log.
a /\ 2.98 0.88
¯_ 2.98
b /\ 3.02 1.29
¯_ 3.02
c /\ 1.91 2.25
¯_ 1.90
xnr3v1x2 schematic xnr3v1x2 standard cell layout