oai23a standard cell family

2-OR and 3-OR into 2-NAND with inverted and shared inputs
oai23a symbol
Minimum sized cell with a P/N ratio of about 2 on the output. Implemented as a 2-NAND followed by an 2x 2-OR into 2-NAND gate (oai22).
z:((b1'*b2')+(a3'*b1*b2)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin b2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oai23av0x05 3.0  72 3.96  0.96   9.8  4.9f  80  7.24  82  4.98
oai23av0x05
 
Effort
FO4 Log.
a3 /\ 1.72 1.76
¯_
b1 /\ 2.66 3.68
¯_ 3.54
b2 /\ 2.40 3.38
¯_ 3.34
oai23av0x05 schematic oai23av0x05 standard cell layout