oai31 standard cell family

3-OR into 2-NAND gate
oai31 symbol
2 cells with a P/N ratio of about 2. The width of the P-transistor connected to pin b is designed to have a similar conductivity to the three series P-transistors in order to maintain a consistent output drive capability.
z:((a1+a2+a3)*b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a3.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oai31v0x05 2.3  56 3.08  0.54   9.8  3.9f  66  6.50  49  4.19
oai31v0x1 3.0  72 3.96 1.00  17.3  7.0f  62  3.37  49  2.35
oai31v0x2 5.7 136 7.48 2.26  35.6 15.1f  60  1.57  50  1.11
oai31v0x05
 
Effort
FO4 Log.
a1 /\ 2.46 2.59
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a2 /\ 2.31 2.51
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a3 /\ 2.03 2.45
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b /\ 1.30 1.26
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oai31v0x05 schematic oai31v0x05 standard cell layout
oai31v0x1
 
Effort
FO4 Log.
a1 /\ 2.49 2.66
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a2 /\ 2.29 2.50
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a3 /\ 1.95 2.35
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b /\ 1.30 1.22
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oai31v0x1 schematic oai31v0x1 standard cell layout
oai31v0x2
 
Effort
FO4 Log.
a1 /\ 2.49 2.66
¯_
a2 /\ 2.29 2.50
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a3 /\ 1.95 2.35
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b /\ 1.24 1.17
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oai31v0x2 schematic oai31v0x2 standard cell layout