oai22 standard cell family

2x 2-OR into 2-NAND gate
oai22 symbol
3 cells with different drive strengths, each with a P/N ratio of about 2. The Ramp Fall time reported below is an average of when one or the other or both of the N-transistors connected to a1 and a2 are on. The Synopsys Liberty format .lib file has the precise timing for each case.
z:((a1+a2)*(b1+b2))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin b2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
wsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oai22v0x05 2.3  56 3.08  0.53   7.0  2.5f  56  7.30  49  4.93
oai22v0x1 2.3  56 3.08  0.95  10.8  4.5f  53  4.33  44  2.75
oai22v0x2 4.0  96 5.28 1.94  21.7  8.7f  53  2.09  44  1.35
oai22v0x05
 
Effort
FO4 Log.
a1 /\ 2.02 1.89
¯_
a2 /\ 1.86 1.85
¯_
b1 /\ 1.85 1.94
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b2 /\ 1.64 1.81
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oai22v0x05 schematic oai22v0x05 standard cell layout
oai22v0x1
 
Effort
FO4 Log.
a1 /\ 1.92 1.80
¯_
a2 /\ 1.75 1.72
¯_
b1 /\ 1.78 1.94
¯_
b2 /\ 1.60 1.84
¯_
oai22v0x1 schematic oai22v0x1 standard cell layout
oai22v0x2
 
Effort
FO4 Log.
a1 /\ 1.89 1.80
¯_
a2 /\ 1.69 1.65
¯_
b1 /\ 1.75 1.90
¯_
b2 /\ 1.55 1.75
¯_
oai22v0x2 schematic oai22v0x2 standard cell layout