xaon21 standard cell family

2-I/P exclusive OR gate with 2-AND input
xaon21 symbol
2 XOR gates with AND gate input designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:((a1*a2)^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xaon21_x05 2.7  80 4.40  0.70  20.5  3.8f  90  4.78  87  3.86
xaon21_x1 2.7  80 4.40 1.35  36.5  7.1f  84  2.50  83  2.06
xaon21_x05
 
Effort
FO4 Log.
a1 /\ 1.84 1.53
¯_ 2.58
a2 /\ 1.84 1.58
¯_ 2.60
b /\ 2.15 2.73
¯_ 1.96
xaon21_x05 schematic xaon21_x05 standard cell layout
xaon21_x1
 
Effort
FO4 Log.
a1 /\ 1.75 1.47
¯_ 2.52
a2 /\ 1.73 1.48
¯_ 2.52
b /\ 2.02 2.56
¯_ 1.88
xaon21_x1 schematic xaon21_x1 standard cell layout