xaon22 standard cell family

2-I/P exclusive OR gate with 2×2-AND inputs
xaon22 symbol
2 XOR gates with each input being a 2-AND gate, designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:((a1*a2)^(b1*b2)) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xaon22_x05 3.3 100 5.50  0.75  25.1  4.3f  95  4.65  91  3.61
xaon22_x1 3.3 100 5.50 1.26  41.6  7.9f  88  2.70  83  1.87
xaon22_x05
 
Effort
FO4 Log.
a1 /\ 2.02 1.65
¯_ 2.67
a2 /\ 2.02 1.72
¯_ 2.69
b1 /\ 2.59 3.19
¯_ 2.38
b2 /\ 2.66 3.25
¯_ 2.42
xaon22_x05 schematic xaon22_x05 standard cell layout
xaon22_x1
 
Effort
FO4 Log.
a1 /\ 2.00 1.76
¯_ 2.57
a2 /\ 1.97 1.80
¯_ 2.56
b1 /\ 2.33 2.75
¯_ 2.16
b2 /\ 2.36 2.76
¯_ 2.16
xaon22_x1 schematic xaon22_x1 standard cell layout