xaoi21 standard cell family

2-I/P exclusive NOR gate with 2-AND input
xaoi21 symbol
2 XNOR gates with AND gate input designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:((a1*a2)^b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xaoi21_x05 2.7  80 4.40  0.70  22.6  3.9f  97  4.77  93  3.89
xaoi21_x1 3.0  90 4.95 1.35  39.6  7.1f  90  2.50  87  2.01
xaoi21_x05
 
Effort
FO4 Log.
a1 /\ 1.98 1.65
¯_ 2.77
a2 /\ 1.94 1.61
¯_ 2.73
b /\ 1.97 2.45
¯_ 2.42
xaoi21_x05 schematic xaoi21_x05 standard cell layout
xaoi21_x1
 
Effort
FO4 Log.
a1 /\ 1.84 1.54
¯_ 2.64
a2 /\ 1.78 1.48
¯_ 2.59
b /\ 1.88 2.36
¯_ 2.26
xaoi21_x1 schematic xaoi21_x1 standard cell layout