or4 standard cell family

4-I/P OR gate
or4 symbol
4 I/P OR gate designed with a large input stage. This reduces the delay, especially when the wire capacitance on the input pin is high.
z:(a+b+c+d) cell width power Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
or4_x1 2.7  80 4.40 1.07  20.7  4.9f  99  2.96 119  2.39
or4_x1
 
Effort
FO4 Log.
a /\
¯_ 3.20
b /\
¯_ 3.03
c /\
¯_ 2.73
d /\
¯_ 2.32
or4_x1 schematic or4_x1 standard cell layout