or3 standard cell family

3-I/P OR gate
or3 symbol
3 I/P OR gate designed with a large input stage. This reduces the delay, especially when the wire capacitance on the input pin is high.
z:(a+b+c) cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
or3_x1 2.0  60 3.30 1.02  20.6  5.0f  89  2.96 107  2.33
or3_x1
 
Effort
FO4 Log.
a /\
¯_ 2.64
b /\
¯_ 2.47
c /\
¯_ 2.16
or3_x1 schematic or3_x1 standard cell layout