or2 standard cell family

2-I/P OR gate
or2 symbol
2 I/P OR gate designed with a large input stage. This reduces the delay, especially when the wire capacitance on the input pin is high.
z:(a+b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
or2_x1 1.7  50 2.75  0.82  17.5  4.1f  77  2.96  90  2.29
FO4 Log.
a /\
¯_ 1.99
b /\
¯_ 1.81
or2_x1 schematic or2_x1 standard cell layout