nr4 standard cell family

4-I/P NOR gate
nr4 symbol
The P/N ratio has been kept as close to 2 as possible for balanced output skew, even if this is not the fastest configuration.
z:(a+b+c+d)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nr4_x05 2.0  60 3.30  0.73   9.8  4.5f  50  5.98  57  3.84
nr4_x1 3.0  90 4.95 1.41  50.5 10.1f 109  2.99  99  2.18
nr4_x05
 
Effort
FO4 Log.
a /\ 2.89 2.83
¯_
b /\ 2.75 2.78
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c /\ 2.48 2.71
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d /\ 2.03 2.57
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nr4_x05 schematic nr4_x05 standard cell layout
nr4_x1
 
Effort
FO4 Log.
a /\ 1.97 2.56
¯_
b /\ 2.75 2.82
¯_
c /\ 2.44 2.72
¯_
d /\ 2.99 3.05
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nr4_x1 schematic nr4_x1 standard cell layout