oai21 standard cell family

2-OR into 2-NAND gate
oai21 symbol
3 cells with different drive strengths, each with a P/N ratio of about 2. The width of the P-transistor connected to pin b is designed to have a similar conductivity to the two series P-transistors, so that there is a consistent output drive capability.
z:((a1+a2)*b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oai21_x05 1.7  50 2.75  0.52   9.8  3.7f  61  5.05  46  3.70
oai21_x1 1.7  50 2.75  0.87  15.7  5.9f  59  2.98  44  2.17
oai21_x2 2.3  70 3.85 1.69  28.3 10.9f  56  1.53  43  1.14
oai21_x05
 
Effort
FO4 Log.
a1 /\ 1.85 1.93
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a2 /\ 1.69 1.88
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b /\ 1.29 1.29
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oai21_x05 schematic oai21_x05 standard cell layout
oai21_x1
 
Effort
FO4 Log.
a1 /\ 1.78 1.85
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a2 /\ 1.60 1.77
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b /\ 1.22 1.18
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oai21_x1 schematic oai21_x1 standard cell layout
oai21_x2
 
Effort
FO4 Log.
a1 /\ 1.75 1.84
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a2 /\ 1.54 1.70
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b /\ 1.19 1.12
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oai21_x2 schematic oai21_x2 standard cell layout