nr3 standard cell family

3-I/P NOR gate
nr3 symbol
The P/N ratio has been kept as close to 2 as possible for balanced output skew, even if this is not the fastest configuration.
z:(a+b+c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nr3_x05 1.7  50 2.75  0.73   9.7  4.9f  49  4.47  49  2.88
nr3_x1 2.3  70 3.85 1.42  16.6  9.2f  44  2.23  47  1.54
nr3_x05
 
Effort
FO4 Log.
a /\ 2.15 2.22
¯_
b /\ 2.02 2.18
¯_
c /\ 1.73 2.09
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nr3_x05 schematic nr3_x05 standard cell layout
nr3_x1
 
Effort
FO4 Log.
a /\ 2.24 2.38
¯_
b /\ 1.99 2.18
¯_
c /\ 1.65 2.03
¯_
nr3_x1 schematic nr3_x1 standard cell layout