aoi21 standard cell family

2-AND into 2-NOR gate
aoi21 symbol
3 cells with different drive strengths, each with a P/N ratio of about 2. The width of the N-transistor connected to pin b is designed to have a similar conductivity to the two series N-transistors in order to maintain a consistent output drive capability.
z:((a1*a2)+b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
aoi21_x05 1.7  50 2.75  0.40  10.9  3.3f  67  5.83  56  4.13
aoi21_x1 1.7  50 2.75  0.76  19.4  6.0f  63  2.99  55  2.18
aoi21_x2 3.0  90 4.95 1.54  35.3 11.5f  59  1.49  53  1.12
aoi21_x05
 
Effort
FO4 Log.
a1 /\ 1.89 1.95
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a2 /\ 1.83 1.94
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b /\ 1.43 1.58
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aoi21_x05 schematic aoi21_x05 standard cell layout
aoi21_x1
 
Effort
FO4 Log.
a1 /\ 1.80 1.86
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a2 /\ 1.74 1.82
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b /\ 1.38 1.50
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aoi21_x1 schematic aoi21_x1 standard cell layout
aoi21_x2
 
Effort
FO4 Log.
a1 /\ 1.77 1.88
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a2 /\ 1.66 1.74
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b /\ 1.28 1.39
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aoi21_x2 schematic aoi21_x2 standard cell layout