aoi22 standard cell family

2×2-AND into 2-NOR gate
aoi22 symbol
3 cells with different drive strengths, each with a P/N ratio of about 2. The Ramp Rise time reported below is an average of when one or the other or both of the P-transistors connected to a1 and a2 are on. The Synopsys Liberty format .lib file has the precise timing for each case.
z:((a1*a2)+(b1*b2))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin b2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
aoi22_x05 2.0  60 3.30  0.67   8.1  3.3f  53  5.31  48  4.09
aoi22_x1 2.0  60 3.30 1.29  14.3  5.8f  50  2.72  46  2.17
aoi22_x2 3.7 110 6.05 2.47  26.8 11.0f  50  1.44  46  1.12
aoi22_x05
 
Effort
FO4 Log.
a1 /\ 2.02 1.85
¯_
a2 /\ 1.99 1.87
¯_
b1 /\ 1.69 1.87
¯_
b2 /\ 1.61 1.80
¯_
aoi22_x05 schematic aoi22_x05 standard cell layout
aoi22_x1
 
Effort
FO4 Log.
a1 /\ 1.92 1.74
¯_
a2 /\ 1.88 1.74
¯_
b1 /\ 1.57 1.71
¯_
b2 /\ 1.51 1.66
¯_
aoi22_x1 schematic aoi22_x1 standard cell layout
aoi22_x2
 
Effort
FO4 Log.
a1 /\ 1.87 1.70
¯_
a2 /\ 1.84 1.70
¯_
b1 /\ 1.51 1.61
¯_
b2 /\ 1.49 1.63
¯_
aoi22_x2 schematic aoi22_x2 standard cell layout