an4 standard cell family

4-I/P AND gate
an4 symbol
4 I/P AND gate designed with a large input stage. This reduces the delay, especially when the wire capacitance on the input pin is high.
z:(a*b*c*d) cell width power Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
an4_x1 2.3  70 3.85 1.30  22.0  4.1f  93  2.98 103  2.29
an4_x2 2.3  70 3.85 1.81  34.7  5.9f  94  1.57 102  1.21
an4_x3 3.0  90 4.95 2.58  42.8  6.9f  96  1.13 103  0.88
an4_x1
 
Effort
FO4 Log.
a /\
¯_ 2.44
b /\
¯_ 2.34
c /\
¯_ 2.19
d /\
¯_ 2.03
an4_x1 schematic an4_x1 standard cell layout
an4_x2
 
Effort
FO4 Log.
a /\
¯_ 2.26
b /\
¯_ 2.16
c /\
¯_ 2.03
d /\
¯_ 1.88
an4_x2 schematic an4_x2 standard cell layout
an4_x3
 
Effort
FO4 Log.
a /\
¯_ 2.19
b /\
¯_ 2.10
c /\
¯_ 1.97
d /\
¯_ 1.82
an4_x3 schematic an4_x3 standard cell layout