an3 standard cell family

3-I/P AND gate
an3 symbol
3 I/P AND gate designed with a large input stage. This reduces the delay, especially when the wire capacitance on the input pin is high.
z:(a*b*c) cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
an3_x1 2.0  60 3.30 1.09  20.2  4.0f  83  2.97  96  2.29
an3_x2 2.0  60 3.30 1.77  32.3  5.7f  83  1.56  96  1.21
an3_x1
 
Effort
FO4 Log.
a /\
¯_ 2.12
b /\
¯_ 1.99
c /\
¯_ 1.88
an3_x1 schematic an3_x1 standard cell layout
an3_x2
 
Effort
FO4 Log.
a /\
¯_ 1.93
b /\
¯_ 1.84
c /\
¯_ 1.73
an3_x2 schematic an3_x2 standard cell layout