an2 standard cell family

2-I/P AND gate
an2 symbol
2 I/P AND gate designed with a large input stage. This reduces the delay, especially when the wire capacitance on the input pin is high. The stage effort is 1.2 for the an2_x05, 1.5 for the an2_x1 and 1.9 for the an2_x2.
z:(a*b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
an2_x05 1.7  50 2.75  0.60  12.0  2.9f  66  4.94  83  3.81
an2_x1 1.7  50 2.75  0.88  17.4  3.8f  65  2.96  85  2.27
an2_x2 1.7  50 2.75 1.48  28.9  5.5f  67  1.56  85  1.20
an2_x05
 
Effort
FO4 Log.
a /\
¯_ 1.90
b /\
¯_ 1.78
an2_x05 schematic an2_x05 standard cell layout
an2_x1
 
Effort
FO4 Log.
a /\
¯_ 1.73
b /\
¯_ 1.64
an2_x1 schematic an2_x1 standard cell layout
an2_x2
 
Effort
FO4 Log.
a /\
¯_ 1.61
b /\
¯_ 1.53
an2_x2 schematic an2_x2 standard cell layout